arc/riscv: get rid of immediate-assignment
diff mbox series

Message ID 20191027112306.346-1-yann.morin.1998@free.fr
State New
Headers show
Series
  • arc/riscv: get rid of immediate-assignment
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Commit Message

Yann E. MORIN Oct. 27, 2019, 11:23 a.m. UTC
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
Cc: Mark Corbin <mark.corbin@embecosm.com>
Cc: Arnout Vandecappelle <arnout@mind.be>

---
Changes v1 -> v2:
  - add MArk in Cc
  - further simplify the code  (Arnout)
---
 arch/arch.mk.riscv | 32 +++++++++++---------------------
 1 file changed, 11 insertions(+), 21 deletions(-)

Comments

Thomas Petazzoni Oct. 27, 2019, 11:45 a.m. UTC | #1
Hello,

arc -> arch in the commit title.

On Sun, 27 Oct 2019 12:23:06 +0100
"Yann E. MORIN" <yann.morin.1998@free.fr> wrote:

>  ifeq ($(BR2_riscv),y)
>  
> -ifeq ($(BR2_RISCV_64),y)
> -GCC_TARGET_ARCH := rv64i
> -else
> -GCC_TARGET_ARCH := rv32i
> -endif
> -
> -ifeq ($(BR2_RISCV_ISA_RVM),y)
> -GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)m
> -endif
> -ifeq ($(BR2_RISCV_ISA_RVA),y)
> -GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)a
> -endif
> -ifeq ($(BR2_RISCV_ISA_RVF),y)
> -GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)f
> -endif
> -ifeq ($(BR2_RISCV_ISA_RVD),y)
> -GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)d
> -endif
> -ifeq ($(BR2_RISCV_ISA_RVC),y)
> -GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
> -endif
> +GCC_TARGET_ARCH = \
> +	$(subst $(space),, \
> +		rv \
> +		$(if $(BR2_RISCV_64),64,32) \
> +		i \
> +		$(if $(BR2_RISCV_ISA_RVM),m) \
> +		$(if $(BR2_RISCV_ISA_RVA),a) \
> +		$(if $(BR2_RISCV_ISA_RVF),f) \
> +		$(if $(BR2_RISCV_ISA_RVD),d) \
> +		$(if $(BR2_RISCV_ISA_RVC),c) \
> +	)

I really don't find this to be an improvement.

The existing code is completely obvious, you don't even have to turn on
your brain to understand what it does. With your change, it becomes a
lot less obvious.

Do we have a justification/motivation for this change ? I.e, what is
the problem with immediate assignment in general ?

Thomas

Patch
diff mbox series

diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
index f3bf2b3467..204e78a57f 100644
--- a/arch/arch.mk.riscv
+++ b/arch/arch.mk.riscv
@@ -5,26 +5,16 @@ 
 
 ifeq ($(BR2_riscv),y)
 
-ifeq ($(BR2_RISCV_64),y)
-GCC_TARGET_ARCH := rv64i
-else
-GCC_TARGET_ARCH := rv32i
-endif
-
-ifeq ($(BR2_RISCV_ISA_RVM),y)
-GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)m
-endif
-ifeq ($(BR2_RISCV_ISA_RVA),y)
-GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)a
-endif
-ifeq ($(BR2_RISCV_ISA_RVF),y)
-GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)f
-endif
-ifeq ($(BR2_RISCV_ISA_RVD),y)
-GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)d
-endif
-ifeq ($(BR2_RISCV_ISA_RVC),y)
-GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
-endif
+GCC_TARGET_ARCH = \
+	$(subst $(space),, \
+		rv \
+		$(if $(BR2_RISCV_64),64,32) \
+		i \
+		$(if $(BR2_RISCV_ISA_RVM),m) \
+		$(if $(BR2_RISCV_ISA_RVA),a) \
+		$(if $(BR2_RISCV_ISA_RVF),f) \
+		$(if $(BR2_RISCV_ISA_RVD),d) \
+		$(if $(BR2_RISCV_ISA_RVC),c) \
+	)
 
 endif