diff mbox series

[PULL,v2,47/73] target/riscv: fetch code with translator_ld

Message ID 20191025063713.23374-48-alex.bennee@linaro.org
State New
Headers show
Series [PULL,v2,01/73] travis.yml: reduce scope of the --enable-debug build | expand

Commit Message

Alex Bennée Oct. 25, 2019, 6:36 a.m. UTC 
From: "Emilio G. Cota" <cota@braap.org>

Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Palmer Dabbelt <palmer@sifive.com>
diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index adeddb85f67..b26533d4fd7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -779,7 +779,7 @@  static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
     CPURISCVState *env = cpu->env_ptr;
 
-    ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
+    ctx->opcode = translator_ldl(env, ctx->base.pc_next);
     decode_opc(ctx);
     ctx->base.pc_next = ctx->pc_succ_insn;