pinctrl: at91: Enable slewrate by default on SAM9X60
diff mbox series

Message ID 20191024172234.5267-1-codrin.ciubotariu@microchip.com
State New
Headers show
Series
  • pinctrl: at91: Enable slewrate by default on SAM9X60
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Commit Message

Codrin Ciubotariu Oct. 24, 2019, 5:22 p.m. UTC
On SAM9X60, slewrate should be enabled on pins with a switching frequency
below 50Mhz. Since most of our pins do not exceed this value, we enable
slewrate by default. Pins with a switching value that exceeds 50Mhz will
have to explicitly disable slewrate.

Suggested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
---
 drivers/pinctrl/pinctrl-at91.c     | 4 ++--
 include/dt-bindings/pinctrl/at91.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

Comments

Rob Herring Oct. 29, 2019, 9:37 p.m. UTC | #1
On Thu, Oct 24, 2019 at 08:22:34PM +0300, Codrin Ciubotariu wrote:
> On SAM9X60, slewrate should be enabled on pins with a switching frequency
> below 50Mhz. Since most of our pins do not exceed this value, we enable
> slewrate by default. Pins with a switching value that exceeds 50Mhz will
> have to explicitly disable slewrate.
> 
> Suggested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
> ---
>  drivers/pinctrl/pinctrl-at91.c     | 4 ++--
>  include/dt-bindings/pinctrl/at91.h | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> index 117075b5798f..c135149e84e9 100644
> --- a/drivers/pinctrl/pinctrl-at91.c
> +++ b/drivers/pinctrl/pinctrl-at91.c
> @@ -85,8 +85,8 @@ enum drive_strength_bit {
>  					 DRIVE_STRENGTH_SHIFT)
>  
>  enum slewrate_bit {
> -	SLEWRATE_BIT_DIS,
>  	SLEWRATE_BIT_ENA,
> +	SLEWRATE_BIT_DIS,
>  };
>  
>  #define SLEWRATE_BIT_MSK(name)		(SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
> @@ -669,7 +669,7 @@ static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
>  {
>  	unsigned int tmp;
>  
> -	if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
> +	if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
>  		return;
>  
>  	tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
> diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
> index 3831f91fb3ba..e8e117306b1b 100644
> --- a/include/dt-bindings/pinctrl/at91.h
> +++ b/include/dt-bindings/pinctrl/at91.h
> @@ -27,8 +27,8 @@
>  #define AT91_PINCTRL_DRIVE_STRENGTH_MED			(0x2 << 5)
>  #define AT91_PINCTRL_DRIVE_STRENGTH_HI			(0x3 << 5)
>  
> -#define AT91_PINCTRL_SLEWRATE_DIS	(0x0 << 9)
> -#define AT91_PINCTRL_SLEWRATE_ENA	(0x1 << 9)
> +#define AT91_PINCTRL_SLEWRATE_ENA	(0x0 << 9)
> +#define AT91_PINCTRL_SLEWRATE_DIS	(0x1 << 9)

This is an ABI. You can't just change the definition.

Rob
Ludovic Desroches Oct. 30, 2019, 8:53 a.m. UTC | #2
On Tue, Oct 29, 2019 at 04:37:57PM -0500, Rob Herring wrote:
> On Thu, Oct 24, 2019 at 08:22:34PM +0300, Codrin Ciubotariu wrote:
> > On SAM9X60, slewrate should be enabled on pins with a switching frequency
> > below 50Mhz. Since most of our pins do not exceed this value, we enable
> > slewrate by default. Pins with a switching value that exceeds 50Mhz will
> > have to explicitly disable slewrate.
> > 
> > Suggested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
> > Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
> > ---
> >  drivers/pinctrl/pinctrl-at91.c     | 4 ++--
> >  include/dt-bindings/pinctrl/at91.h | 4 ++--
> >  2 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> > index 117075b5798f..c135149e84e9 100644
> > --- a/drivers/pinctrl/pinctrl-at91.c
> > +++ b/drivers/pinctrl/pinctrl-at91.c
> > @@ -85,8 +85,8 @@ enum drive_strength_bit {
> >  					 DRIVE_STRENGTH_SHIFT)
> >  
> >  enum slewrate_bit {
> > -	SLEWRATE_BIT_DIS,
> >  	SLEWRATE_BIT_ENA,
> > +	SLEWRATE_BIT_DIS,
> >  };
> >  
> >  #define SLEWRATE_BIT_MSK(name)		(SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
> > @@ -669,7 +669,7 @@ static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
> >  {
> >  	unsigned int tmp;
> >  
> > -	if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
> > +	if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
> >  		return;
> >  
> >  	tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
> > diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
> > index 3831f91fb3ba..e8e117306b1b 100644
> > --- a/include/dt-bindings/pinctrl/at91.h
> > +++ b/include/dt-bindings/pinctrl/at91.h
> > @@ -27,8 +27,8 @@
> >  #define AT91_PINCTRL_DRIVE_STRENGTH_MED			(0x2 << 5)
> >  #define AT91_PINCTRL_DRIVE_STRENGTH_HI			(0x3 << 5)
> >  
> > -#define AT91_PINCTRL_SLEWRATE_DIS	(0x0 << 9)
> > -#define AT91_PINCTRL_SLEWRATE_ENA	(0x1 << 9)
> > +#define AT91_PINCTRL_SLEWRATE_ENA	(0x0 << 9)
> > +#define AT91_PINCTRL_SLEWRATE_DIS	(0x1 << 9)
> 
> This is an ABI. You can't just change the definition.

There is no DT using these definitions. They have been introduced for our new
SoC but its DT is not submitted yet. I assume it's not too late to do this
change as nothing will be broken.

Regards

Ludovic

> 
> Rob
Rob Herring Oct. 30, 2019, 1:15 p.m. UTC | #3
On Wed, Oct 30, 2019 at 3:53 AM Ludovic Desroches
<ludovic.desroches@microchip.com> wrote:
>
> On Tue, Oct 29, 2019 at 04:37:57PM -0500, Rob Herring wrote:
> > On Thu, Oct 24, 2019 at 08:22:34PM +0300, Codrin Ciubotariu wrote:
> > > On SAM9X60, slewrate should be enabled on pins with a switching frequency
> > > below 50Mhz. Since most of our pins do not exceed this value, we enable
> > > slewrate by default. Pins with a switching value that exceeds 50Mhz will
> > > have to explicitly disable slewrate.
> > >
> > > Suggested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
> > > Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
> > > ---
> > >  drivers/pinctrl/pinctrl-at91.c     | 4 ++--
> > >  include/dt-bindings/pinctrl/at91.h | 4 ++--
> > >  2 files changed, 4 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> > > index 117075b5798f..c135149e84e9 100644
> > > --- a/drivers/pinctrl/pinctrl-at91.c
> > > +++ b/drivers/pinctrl/pinctrl-at91.c
> > > @@ -85,8 +85,8 @@ enum drive_strength_bit {
> > >                                      DRIVE_STRENGTH_SHIFT)
> > >
> > >  enum slewrate_bit {
> > > -   SLEWRATE_BIT_DIS,
> > >     SLEWRATE_BIT_ENA,
> > > +   SLEWRATE_BIT_DIS,
> > >  };
> > >
> > >  #define SLEWRATE_BIT_MSK(name)             (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
> > > @@ -669,7 +669,7 @@ static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
> > >  {
> > >     unsigned int tmp;
> > >
> > > -   if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
> > > +   if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
> > >             return;
> > >
> > >     tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
> > > diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
> > > index 3831f91fb3ba..e8e117306b1b 100644
> > > --- a/include/dt-bindings/pinctrl/at91.h
> > > +++ b/include/dt-bindings/pinctrl/at91.h
> > > @@ -27,8 +27,8 @@
> > >  #define AT91_PINCTRL_DRIVE_STRENGTH_MED                    (0x2 << 5)
> > >  #define AT91_PINCTRL_DRIVE_STRENGTH_HI                     (0x3 << 5)
> > >
> > > -#define AT91_PINCTRL_SLEWRATE_DIS  (0x0 << 9)
> > > -#define AT91_PINCTRL_SLEWRATE_ENA  (0x1 << 9)
> > > +#define AT91_PINCTRL_SLEWRATE_ENA  (0x0 << 9)
> > > +#define AT91_PINCTRL_SLEWRATE_DIS  (0x1 << 9)
> >
> > This is an ABI. You can't just change the definition.
>
> There is no DT using these definitions. They have been introduced for our new
> SoC but its DT is not submitted yet. I assume it's not too late to do this
> change as nothing will be broken.

Okay, then state this in the commit message.

Rob

Patch
diff mbox series

diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 117075b5798f..c135149e84e9 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -85,8 +85,8 @@  enum drive_strength_bit {
 					 DRIVE_STRENGTH_SHIFT)
 
 enum slewrate_bit {
-	SLEWRATE_BIT_DIS,
 	SLEWRATE_BIT_ENA,
+	SLEWRATE_BIT_DIS,
 };
 
 #define SLEWRATE_BIT_MSK(name)		(SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
@@ -669,7 +669,7 @@  static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
 {
 	unsigned int tmp;
 
-	if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
+	if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
 		return;
 
 	tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
index 3831f91fb3ba..e8e117306b1b 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -27,8 +27,8 @@ 
 #define AT91_PINCTRL_DRIVE_STRENGTH_MED			(0x2 << 5)
 #define AT91_PINCTRL_DRIVE_STRENGTH_HI			(0x3 << 5)
 
-#define AT91_PINCTRL_SLEWRATE_DIS	(0x0 << 9)
-#define AT91_PINCTRL_SLEWRATE_ENA	(0x1 << 9)
+#define AT91_PINCTRL_SLEWRATE_ENA	(0x0 << 9)
+#define AT91_PINCTRL_SLEWRATE_DIS	(0x1 << 9)
 
 #define AT91_PIOA	0
 #define AT91_PIOB	1