| Message ID | 9b53139b7043572b3846a214694dbf8fe1f56f50.1571915550.git.matti.vaittinen@fi.rohmeurope.com |
|---|---|
| State | New |
| Headers | show |
| Series | Support ROHM BD71828 PMIC | expand |
Hi Matti, Thanks for your patch! On Thu, Oct 24, 2019 at 1:51 PM Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> wrote: > ROHM BD71828 PMIC contains 4 pins which can be configured by OTP > to be used for general purposes. First 3 can be used as outputs > and 4.th pin can be used as input. Allow them to be controlled > via GPIO framework. > > The driver assumes all of the pins are configured as GPIOs and > trusts that the reserved pins in other OTP configurations are > excluded from control using "gpio-reserved-ranges" device tree > property (or left untouched by GPIO users). > > Typical use for 4.th pin (input) is to use it as HALL sensor > input so that this pin state is toggled when HALL sensor detects > LID position change (from close to open or open to close). PMIC > HW implements some extra logic which allows PMIC to power-up the > system when this pin is toggled. Please see the data sheet for > details of GPIO options which can be selcted by OTP settings. spelling of selected > Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Overall looks very good. > +// SPDX-License-Identifier: GPL-2.0 I think they want you to use GPL-2.0-only these days. > +#define BD71828_OUT 0 > +#define BD71828_IN 1 These have nothing to do with BD71828, just skip these defines and hardcode 0/1 in the code called from gpiolib. If we want defines for this they should be generically named and put in <linux/gpio/driver.h> Nice use of the config API! Yours, Linus Walleij
Hello Linus, Thanks again for the review :) Highly appreciated! On Thu, 2019-10-24 at 13:59 +0200, Linus Walleij wrote: > On Thu, Oct 24, 2019 at 1:51 PM Matti Vaittinen > <matti.vaittinen@fi.rohmeurope.com> wrote: > > > ROHM BD71828 PMIC contains 4 pins which can be configured by OTP > > to be used for general purposes. First 3 can be used as outputs > > and 4.th pin can be used as input. Allow them to be controlled > > via GPIO framework. > > > > The driver assumes all of the pins are configured as GPIOs and > > trusts that the reserved pins in other OTP configurations are > > excluded from control using "gpio-reserved-ranges" device tree > > property (or left untouched by GPIO users). > > > > Typical use for 4.th pin (input) is to use it as HALL sensor > > input so that this pin state is toggled when HALL sensor detects > > LID position change (from close to open or open to close). PMIC > > HW implements some extra logic which allows PMIC to power-up the > > system when this pin is toggled. Please see the data sheet for > > details of GPIO options which can be selcted by OTP settings. > > spelling of selected Right, thanks. > > Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> > > Overall looks very good. > > > +// SPDX-License-Identifier: GPL-2.0 > > I think they want you to use GPL-2.0-only these days. Hmm. Is this documented somewhere? The LICENSES/preferred/GPL-2.0 still states: Valid-License-Identifier: GPL-2.0 Valid-License-Identifier: GPL-2.0-only Valid-License-Identifier: GPL-2.0+ Valid-License-Identifier: GPL-2.0-or-later SPDX-URL: https://spdx.org/licenses/GPL-2.0.html Usage-Guide: To use this license in source code, put one of the following SPDX tag/value pairs into a comment according to the placement guidelines in the licensing rules documentation. For 'GNU General Public License (GPL) version 2 only' use: SPDX-License-Identifier: GPL-2.0 or SPDX-License-Identifier: GPL-2.0-only For 'GNU General Public License (GPL) version 2 or any later version' use: SPDX-License-Identifier: GPL-2.0+ or SPDX-License-Identifier: GPL-2.0-or-later (at least for 5.4-rc2) This looks like "GPL-2.0" should still be valid. Not that I have anything against the "GPL-2.0-only" - I am just a tiny bit frustrated what comes to polishing the SPDX format :/ > > +#define BD71828_OUT 0 > > +#define BD71828_IN 1 > > These have nothing to do with BD71828, just skip these defines > and hardcode 0/1 in the code called from gpiolib. I personally don't like using 0/1 as I _always_ need to check which is IN and which is OUT. It must be somehow related to my brain chemistry but this just does not stay in my mind over a weekend... But you are right - having these defines in bd71828 driver does not help much. When I start with next GPIO chip I must once again dig the values from these defines or from somewhere else. Thus... > If we want defines > for this they should be generically named and put in > <linux/gpio/driver.h> ...placing the defines in this header which is visible also in next driver would be "the right thing to do"(tm). Do you think we should add the defines there then? I was not trying to do that as I thought that someone really loves the raw numbers and dislikes defines - as these hard-coded values 1 and 0 seem to be used everywhere... :] Maybe the plain numbers are only difficult for me? > Nice use of the config API! Thanks =) I admit I have stolen that from some other driver. So I don't really deserve the credits =) It's easy to build when the foundations are done well ;) Br, Matti Vaittinen
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index bb13c266c329..fb0a099de961 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -986,6 +986,18 @@ config GPIO_BD70528 This driver can also be built as a module. If so, the module will be called gpio-bd70528. +config GPIO_BD71828 + tristate "ROHM BD71828 GPIO support" + depends on MFD_ROHM_BD71828 + help + Support for GPIOs on ROHM BD71828 PMIC. There are three GPIOs + available on the ROHM PMIC in total. The GPIOs are limited to + outputs only and pins must be configured to GPIO outputs by + OTP. Enable this only if you want to use these pins as outputs. + + This driver can also be built as a module. If so, the module + will be called gpio-bd71828. + config GPIO_BD9571MWV tristate "ROHM BD9571 GPIO support" depends on MFD_BD9571MWV diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index a4e91175c708..b11932844768 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o obj-$(CONFIG_GPIO_BD70528) += gpio-bd70528.o +obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o diff --git a/drivers/gpio/gpio-bd71828.c b/drivers/gpio/gpio-bd71828.c new file mode 100644 index 000000000000..0ec3a1d9adc0 --- /dev/null +++ b/drivers/gpio/gpio-bd71828.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 ROHM Semiconductors + +#include <linux/gpio/driver.h> +#include <linux/mfd/rohm-bd71828.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#define BD71828_OUT 0 +#define BD71828_IN 1 +#define GPIO_OUT_REG(off) (BD71828_REG_GPIO_CTRL1 + (off)) +#define HALL_GPIO_OFFSET 3 + +struct bd71828_gpio { + struct rohm_regmap_dev chip; + struct gpio_chip gpio; +}; + +static void bd71828_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + int ret; + struct bd71828_gpio *bdgpio = gpiochip_get_data(chip); + u8 val = (value) ? BD71828_GPIO_OUT_HI : BD71828_GPIO_OUT_LO; + + /* + * The HALL input pin can only be used as input. If this is the pin + * we are dealing with - then we are done + */ + if (offset == HALL_GPIO_OFFSET) + return; + + ret = regmap_update_bits(bdgpio->chip.regmap, GPIO_OUT_REG(offset), + BD71828_GPIO_OUT_MASK, val); + if (ret) + dev_err(bdgpio->chip.dev, "Could not set gpio to %d\n", value); +} + +static int bd71828_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + int ret; + unsigned int val; + struct bd71828_gpio *bdgpio = gpiochip_get_data(chip); + + if (offset == HALL_GPIO_OFFSET) + ret = regmap_read(bdgpio->chip.regmap, BD71828_REG_IO_STAT, + &val); + else + ret = regmap_read(bdgpio->chip.regmap, GPIO_OUT_REG(offset), + &val); + if (!ret) + ret = (val & BD71828_GPIO_OUT_MASK); + + return ret; +} + +static int bd71828_gpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + struct bd71828_gpio *bdgpio = gpiochip_get_data(chip); + + if (offset == HALL_GPIO_OFFSET) + return -ENOTSUPP; + + switch (pinconf_to_config_param(config)) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + return regmap_update_bits(bdgpio->chip.regmap, + GPIO_OUT_REG(offset), + BD71828_GPIO_DRIVE_MASK, + BD71828_GPIO_OPEN_DRAIN); + case PIN_CONFIG_DRIVE_PUSH_PULL: + return regmap_update_bits(bdgpio->chip.regmap, + GPIO_OUT_REG(offset), + BD71828_GPIO_DRIVE_MASK, + BD71828_GPIO_PUSH_PULL); + default: + break; + } + return -ENOTSUPP; +} + +static int bd71828_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + /* + * Pin usage is selected by OTP data. We can't read it runtime. Hence + * we trust that if the pin is not excluded by "gpio-reserved-ranges" + * the OTP configuration is set to OUT. (Other pins but HALL input pin + * on BD71828 can't really be used for general purpose input - input + * states are used for specific cases like regulator control or + * PMIC_ON_REQ. + */ + if (offset == HALL_GPIO_OFFSET) + return BD71828_IN; + + return BD71828_OUT; +} + +static int bd71828_probe(struct platform_device *pdev) +{ + struct bd71828_gpio *bdgpio; + struct rohm_regmap_dev *bd71828; + + bd71828 = dev_get_drvdata(pdev->dev.parent); + if (!bd71828) { + dev_err(&pdev->dev, "No MFD driver data\n"); + return -EINVAL; + } + + bdgpio = devm_kzalloc(&pdev->dev, sizeof(*bdgpio), + GFP_KERNEL); + if (!bdgpio) + return -ENOMEM; + + bdgpio->chip.dev = &pdev->dev; + bdgpio->gpio.parent = pdev->dev.parent; + bdgpio->gpio.label = "bd71828-gpio"; + bdgpio->gpio.owner = THIS_MODULE; + bdgpio->gpio.get_direction = bd71828_get_direction; + bdgpio->gpio.set_config = bd71828_gpio_set_config; + bdgpio->gpio.can_sleep = true; + bdgpio->gpio.get = bd71828_gpio_get; + bdgpio->gpio.set = bd71828_gpio_set; + bdgpio->gpio.base = -1; + + /* + * See if we need some implementation to mark some PINs as + * not controllable based on DT info or if core can handle + * "gpio-reserved-ranges" and exclude them from control + */ + bdgpio->gpio.ngpio = 4; + bdgpio->gpio.of_node = pdev->dev.parent->of_node; + bdgpio->chip.regmap = bd71828->regmap; + + return devm_gpiochip_add_data(&pdev->dev, &bdgpio->gpio, + bdgpio); +} + +static struct platform_driver bd71828_gpio = { + .driver = { + .name = "bd71828-gpio" + }, + .probe = bd71828_probe, +}; + +module_platform_driver(bd71828_gpio); + +MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); +MODULE_DESCRIPTION("BD71828 voltage regulator driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:bd71828-gpio");
ROHM BD71828 PMIC contains 4 pins which can be configured by OTP to be used for general purposes. First 3 can be used as outputs and 4.th pin can be used as input. Allow them to be controlled via GPIO framework. The driver assumes all of the pins are configured as GPIOs and trusts that the reserved pins in other OTP configurations are excluded from control using "gpio-reserved-ranges" device tree property (or left untouched by GPIO users). Typical use for 4.th pin (input) is to use it as HALL sensor input so that this pin state is toggled when HALL sensor detects LID position change (from close to open or open to close). PMIC HW implements some extra logic which allows PMIC to power-up the system when this pin is toggled. Please see the data sheet for details of GPIO options which can be selcted by OTP settings. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> --- Mainly styling fixes since v1. drivers/gpio/Kconfig | 12 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-bd71828.c | 151 ++++++++++++++++++++++++++++++++++++ 3 files changed, 164 insertions(+) create mode 100644 drivers/gpio/gpio-bd71828.c