diff mbox

[v2,12/23] i8259: Clear ELCR on reset

Message ID 74baaa8accb9bc5fe85988638a8918a33d426a11.1317971994.git.jan.kiszka@siemens.com
State New
Headers show

Commit Message

Jan Kiszka Oct. 7, 2011, 7:19 a.m. UTC 
The ELCR is actually part of the chipset but we model it here for
simplicity reasons. The PIIX3 clears the ELCR on reset, which was once
broken by 4dbe19e181. Fix this by splitting up pic_init_reset from
pic_reset and clearing the register in the latter.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 hw/i8259.c |   15 ++++++++++-----
 1 files changed, 10 insertions(+), 5 deletions(-)
diff mbox

Patch

diff --git a/hw/i8259.c b/hw/i8259.c
index 3498c6b..d18fc62 100644
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -263,10 +263,8 @@  int pic_read_irq(PicState2 *s)
     return intno;
 }
 
-static void pic_reset(void *opaque)
+static void pic_init_reset(PicState *s)
 {
-    PicState *s = opaque;
-
     s->last_irr = 0;
     s->irr = 0;
     s->imr = 0;
@@ -286,6 +284,14 @@  static void pic_reset(void *opaque)
     pic_update_irq(s->pics_state);
 }
 
+static void pic_reset(void *opaque)
+{
+    PicState *s = opaque;
+
+    pic_init_reset(s);
+    s->elcr = 0;
+}
+
 static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
                              uint64_t val64, unsigned size)
 {
@@ -297,8 +303,7 @@  static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
     DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
     if (addr == 0) {
         if (val & 0x10) {
-            /* init */
-            pic_reset(s);
+            pic_init_reset(s);
             s->init_state = 1;
             s->init4 = val & 1;
             s->single_mode = val & 2;