| Message ID | 20191023073622.18430-3-kever.yang@rock-chips.com |
|---|---|
| State | Accepted |
| Commit | ae2500f89a8de636a2a23187010fa57f44ac3bd3 |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | rockchip: adapt SPL in first 0x40000 of DRAM to load ATF | expand |
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 37610774c1..44759f2199 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 3ab0af1158..375b2ec6b3 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3328=y CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, and when we introduce the TPL, the SPL space is in DRAM, we reserve space to avoid SPL text overlap with ATF bl31. Now we decide to move ATF entry point to 0x40000 instead of 0x1000, so that the SPL can have 0x4000 as code size and no need to reserve space or relocate before loading ATF. The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> --- Changes in v3: None Changes in v2: None configs/evb-rk3328_defconfig | 1 - configs/rock64-rk3328_defconfig | 1 - 2 files changed, 2 deletions(-)