From patchwork Thu Oct 6 13:17:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernd Schmidt X-Patchwork-Id: 118095 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 8D547B70B1 for ; Fri, 7 Oct 2011 00:18:07 +1100 (EST) Received: (qmail 4112 invoked by alias); 6 Oct 2011 13:18:02 -0000 Received: (qmail 3987 invoked by uid 22791); 6 Oct 2011 13:18:00 -0000 X-SWARE-Spam-Status: No, hits=-1.0 required=5.0 tests=AWL, BAYES_00, FROM_12LTRDOM X-Spam-Check-By: sourceware.org Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 06 Oct 2011 13:17:38 +0000 Received: from nat-ies.mentorg.com ([192.94.31.2] helo=EU1-MAIL.mgc.mentorg.com) by relay1.mentorg.com with esmtp id 1RBnpR-0003xW-Jm from Bernd_Schmidt@mentor.com for gcc-patches@gcc.gnu.org; Thu, 06 Oct 2011 06:17:37 -0700 Received: from [127.0.0.1] ([172.16.63.104]) by EU1-MAIL.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 6 Oct 2011 14:17:35 +0100 Message-ID: <4E8DAA6C.7010402@codesourcery.com> Date: Thu, 06 Oct 2011 15:17:32 +0200 From: Bernd Schmidt User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.20) Gecko/20110920 Lightning/1.0b3pre Thunderbird/3.1.12 MIME-Version: 1.0 To: GCC Patches Subject: ARM: Fix PR49049 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This corrects a brain fart in one of my patches last year: I added another alternative to a subsi for subtraction of a constant. This is bogus because such an operation should be canonicalized to a PLUS with the negative constant, Normally that's what happens, and so testing never showed that the alternative was only half-finished and didn't work. PR49049 is a testcase where we do end up replacing a REG with a constant and produce the bad alternative, leading to a crash. Tested on arm-eabi and committed as obvious. Will do some sanity checks on 4.6 and commit there as well. Bernd Index: gcc/ChangeLog =================================================================== --- gcc/ChangeLog (revision 179606) +++ gcc/ChangeLog (working copy) @@ -1,3 +1,8 @@ +2011-10-06 Bernd Schmidt + + PR target/49049 + * config/arm/arm.md (arm_subsi3_insn): Lose the last alternative. + 2011-10-06 Ulrich Weigand PR target/50305 Index: gcc/testsuite/gcc.c-torture/compile/pr49049.c =================================================================== --- gcc/testsuite/gcc.c-torture/compile/pr49049.c (revision 0) +++ gcc/testsuite/gcc.c-torture/compile/pr49049.c (revision 0) @@ -0,0 +1,28 @@ +__extension__ typedef unsigned long long int uint64_t; + +static int +sub (int a, int b) +{ + return a - b; +} + +static uint64_t +add (uint64_t a, uint64_t b) +{ + return a + b; +} + +int *ptr; + +int +foo (uint64_t arg1, int *arg2) +{ + int j; + for (; j < 1; j++) + { + *arg2 |= sub ( sub (sub (j || 1 ^ 0x1, 1), arg1 < 0x1 <= + sub (1, *ptr & j)), + (sub ( j != 1 || sub (j && j, 1) >= 0, + add (!j > arg1, 0x35DLL)))); + } +} Index: gcc/testsuite/ChangeLog =================================================================== --- gcc/testsuite/ChangeLog (revision 179606) +++ gcc/testsuite/ChangeLog (working copy) @@ -1,3 +1,8 @@ +2011-10-06 Bernd Schmidt + + PR target/49049 + * gcc.c-torture/compile/pr49049.c: New test. + 2011-10-06 Ulrich Weigand PR target/50305 Index: gcc/config/arm/arm.md =================================================================== --- gcc/config/arm/arm.md (revision 179606) +++ gcc/config/arm/arm.md (working copy) @@ -1213,27 +1213,24 @@ (define_insn "thumb1_subsi3_insn" ; ??? Check Thumb-2 split length (define_insn_and_split "*arm_subsi3_insn" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,rk,r,r") - (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,k,?n,r") - (match_operand:SI 2 "reg_or_int_operand" "r,rI,r, r,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=r,r,rk,r") + (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,k,?n") + (match_operand:SI 2 "reg_or_int_operand" "r,rI,r, r")))] "TARGET_32BIT" "@ rsb%?\\t%0, %2, %1 sub%?\\t%0, %1, %2 sub%?\\t%0, %1, %2 - # #" - "&& ((GET_CODE (operands[1]) == CONST_INT - && !const_ok_for_arm (INTVAL (operands[1]))) - || (GET_CODE (operands[2]) == CONST_INT - && !const_ok_for_arm (INTVAL (operands[2]))))" + "&& (GET_CODE (operands[1]) == CONST_INT + && !const_ok_for_arm (INTVAL (operands[1])))" [(clobber (const_int 0))] " arm_split_constant (MINUS, SImode, curr_insn, INTVAL (operands[1]), operands[0], operands[2], 0); DONE; " - [(set_attr "length" "4,4,4,16,16") + [(set_attr "length" "4,4,4,16") (set_attr "predicable" "yes")] )