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Mon, 21 Oct 2019 20:11:53 +0530 (IST) From: Sai Pavan Boddu To: Alistair Francis Subject: [QEMU][PATCH v4] ssi: xilinx_spips: Skip spi bus update for a few register writes Date: Mon, 21 Oct 2019 20:11:51 +0530 Message-Id: <1571668911-8312-1-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(39860400002)(396003)(376002)(346002)(136003)(199004)(189003)(106002)(305945005)(316002)(8676002)(50226002)(48376002)(70206006)(14444005)(16586007)(42186006)(51416003)(54906003)(8936002)(81156014)(81166006)(103686004)(70586007)(478600001)(50466002)(336012)(26005)(47776003)(4326008)(426003)(486006)(2906002)(2616005)(36756003)(15650500001)(126002)(356004)(186003)(6266002)(6916009)(476003)(5660300002); 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB4790 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.72.89 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, Peter Maydell , qemu-devel@nongnu.org, Francisco Iglesias Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" A few of the register writes need not update the spi bus state, so just return after reg write. Added few more dummy register offsets which need the same behaviour. Signed-off-by: Sai Pavan Boddu --- Changes for V2: Just skip update of spips cs and fifos Update commit message accordingly Changes for V3: Avoid checking for zynqmp qspi Skip spi bus update for few of the registers Changes for V4: Move the register list to existing switch case above. hw/ssi/xilinx_spips.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index a309c71..0d6c2e1 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -109,6 +109,7 @@ #define R_GPIO (0x30 / 4) #define R_LPBK_DLY_ADJ (0x38 / 4) #define R_LPBK_DLY_ADJ_RESET (0x33) +#define R_IOU_TAPDLY_BYPASS (0x3C / 4) #define R_TXD1 (0x80 / 4) #define R_TXD2 (0x84 / 4) #define R_TXD3 (0x88 / 4) @@ -139,6 +140,8 @@ #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) +#define R_DUMMY_CYCLE_EN (0xC8 / 4) +#define R_ECO (0xF8 / 4) #define R_MOD_ID (0xFC / 4) #define R_GQSPI_SELECT (0x144 / 4) @@ -970,6 +973,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, { int mask = ~0; XilinxSPIPS *s = opaque; + bool try_flush = true; DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); addr >>= 2; @@ -1019,13 +1023,23 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; + /* Skip SPI bus update for below registers writes */ + case R_GPIO: + case R_LPBK_DLY_ADJ: + case R_IOU_TAPDLY_BYPASS: + case R_DUMMY_CYCLE_EN: + case R_ECO: + try_flush = false; + break; } s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); no_reg_update: - xilinx_spips_update_cs_lines(s); - xilinx_spips_check_flush(s); - xilinx_spips_update_cs_lines(s); - xilinx_spips_update_ixr(s); + if (try_flush) { + xilinx_spips_update_cs_lines(s); + xilinx_spips_check_flush(s); + xilinx_spips_update_cs_lines(s); + xilinx_spips_update_ixr(s); + } } static const MemoryRegionOps spips_ops = {