From patchwork Mon Oct 21 13:50:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 1180619 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UVOLSzGo"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46xdMk2xScz9sP6 for ; Tue, 22 Oct 2019 00:51:14 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CE3A1C21DAF; Mon, 21 Oct 2019 13:50:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 21618C21E3A; Mon, 21 Oct 2019 13:50:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 38FA0C21E53; Mon, 21 Oct 2019 13:50:45 +0000 (UTC) Received: from mail-qk1-f196.google.com (mail-qk1-f196.google.com [209.85.222.196]) by lists.denx.de (Postfix) with ESMTPS id 73EC6C21DB3 for ; Mon, 21 Oct 2019 13:50:43 +0000 (UTC) Received: by mail-qk1-f196.google.com with SMTP id f18so12042449qkm.1 for ; Mon, 21 Oct 2019 06:50:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2LfUHpGgKaLjyKbFmgSh6XKe7/EjK/tHDrVMSTVckp0=; b=UVOLSzGowCK/tcmBoVeZtwjl2NWHYnynifyqLpOrDqvYTrj4raTV6PMHqWXZwgJ86t vaK3YkXzD4FlWggkKiUo8z4P7M6AcchFQpaEBNw2YwKN+hpH/iv4z8jNo0RwTWY0WzDi p5X3lHUT3fDySgTFjqGPxB8onN0jQRwqamBCRwU8l59wnQ/AdgOolAxGUZ+/cf9buLRU ESNs25vyCIbqbMlTKGWwkZ+rV8cDtI5+wNLLeipVGR4KURsTcVmRJcFIvbilQIpQS2wl 81g5SXFsHR7jAJSWg3ENtKLc8pvNjqqOyQA3O1kXh6VwXnTGXNhAOQnF/f+C0tNJ7Ymf Ud1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2LfUHpGgKaLjyKbFmgSh6XKe7/EjK/tHDrVMSTVckp0=; b=EbjhgJpBRT9wtPN+i68OL+ZZj6vn/4r0xw7+76xrSOxkhjgN1PNUQBqoupeKO0iW0Z CPUHXBTCVE4nCgWmVu7peFAsD0V5hvtp5Oot/S7oDXZOvXl+8dRybMyGihE/5kO/CXZx R2LGqtVrMjiVebGJGeoJHHHNA6JI0pgaFJNZJfeMFCte4J6A8tQ6xpKOS2Fuo2hqm9O6 a6QORIuGcvM/sOBWiSZjR0y43m3G3S6aqTtSbelQeVfdtHilbaldJhRCyocf/gvhsUB2 Y4Qpx4vUeEjTyjFfus9WavIQGKyM1mogE/1aMV6eGlJ/CV+iy5cKEb8QMEMfkM/ZI3PL nkEQ== X-Gm-Message-State: APjAAAVH2SDflQ9AuaEpOAPAv3PjlbWhrMW3QrQGxSpbIuQ4SwAOLewF OVskCVXYk/p7eioSG/UHmd0= X-Google-Smtp-Source: APXvYqxUht4A4OKww3dCXWQdekxJbJhS5Pr4FznNmTCPVs3kwJMzf9SfBag+QR1NObM8rqGYUBy8bw== X-Received: by 2002:a37:4d88:: with SMTP id a130mr15118951qkb.28.1571665842159; Mon, 21 Oct 2019 06:50:42 -0700 (PDT) Received: from localhost.localdomain ([2804:14c:482:99::3]) by smtp.gmail.com with ESMTPSA id 92sm7934125qte.30.2019.10.21.06.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Oct 2019 06:50:41 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Date: Mon, 21 Oct 2019 10:50:29 -0300 Message-Id: <20191021135034.18677-2-festevam@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191021135034.18677-1-festevam@gmail.com> References: <20191021135034.18677-1-festevam@gmail.com> Cc: u-boot@lists.denx.de, uboot-imx@nxp.com Subject: [U-Boot] [PATCH 2/7] mx7ulp: Introduce the CONFIG_LDO_ENABLED_MODE option X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Introduce the CONFIG_LDO_ENABLED_MODE option so that i.MX7ULP boards designed to operate with LDO enabled mode can work with 0.95V at LDO output in RUN mode as per the datasheet. Signed-off-by: Fabio Estevam --- arch/arm/mach-imx/mx7ulp/Kconfig | 5 +++ arch/arm/mach-imx/mx7ulp/soc.c | 58 ++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig index ed5f0aeb2d..138c58363f 100644 --- a/arch/arm/mach-imx/mx7ulp/Kconfig +++ b/arch/arm/mach-imx/mx7ulp/Kconfig @@ -3,6 +3,11 @@ if ARCH_MX7ULP config SYS_SOC default "mx7ulp" +config LDO_ENABLED_MODE + bool "i.MX7ULP LDO Enabled Mode" + help + Select this option to enable the PMC1 LDO. + config MX7ULP bool diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index b9a108a514..751575c95e 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -9,6 +9,22 @@ #include #include +#define PMC0_BASE_ADDR 0x410a1000 +#define PMC0_CTRL 0x28 +#define PMC0_CTRL_LDOEN BIT(31) +#define PMC0_CTRL_LDOOKDIS BIT(30) +#define PMC0_CTRL_PMC1ON BIT(24) +#define PMC1_BASE_ADDR 0x40400000 +#define PMC1_RUN 0x8 +#define PMC1_STOP 0x10 +#define PMC1_VLPS 0x14 +#define PMC1_RUN_LDOVL_SHIFT 16 +#define PMC1_RUN_LDOVL_MASK (0x3f << PMC1_RUN_LDOVL_SHIFT) +#define PMC1_RUN_LDOVL_900 0x1e +#define PMC1_RUN_LDOVL_950 0x23 +#define PMC1_STATUS 0x20 +#define PMC1_STATUS_LDOVLF BIT(8) + static char *get_reset_cause(char *); #if defined(CONFIG_IMX_HAB) @@ -100,6 +116,44 @@ void init_wdog(void) disable_wdog(WDG2_RBASE); } +#if defined(CONFIG_LDO_ENABLED_MODE) +static void init_ldo_mode(void) +{ + unsigned int reg; + + /* Set LDOOKDIS */ + setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); + + /* Set LDOVL to 0.95V in PMC1_RUN */ + reg = readl(PMC1_BASE_ADDR + PMC1_RUN); + reg &= ~PMC1_RUN_LDOVL_MASK; + reg |= (PMC1_RUN_LDOVL_950 << PMC1_RUN_LDOVL_SHIFT); + writel(PMC1_BASE_ADDR + PMC1_RUN, reg); + + /* Wait for LDOVLF to be cleared */ + reg = readl(PMC1_BASE_ADDR + PMC1_STATUS); + while (reg & PMC1_STATUS_LDOVLF) + ; + + /* Set LDOVL to 0.95V in PMC1_STOP */ + reg = readl(PMC1_BASE_ADDR + PMC1_STOP); + reg &= ~PMC1_RUN_LDOVL_MASK; + reg |= (PMC1_RUN_LDOVL_950 << PMC1_RUN_LDOVL_SHIFT); + writel(PMC1_BASE_ADDR + PMC1_STOP, reg); + + /* Set LDOVL to 0.90V in PMC1_VLPS */ + reg = readl(PMC1_BASE_ADDR + PMC1_VLPS); + reg &= ~PMC1_RUN_LDOVL_MASK; + reg |= (PMC1_RUN_LDOVL_900 << PMC1_RUN_LDOVL_SHIFT); + writel(PMC1_BASE_ADDR + PMC1_VLPS, reg); + + /* Set LDOEN bit */ + setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); + + /* Set the PMC1ON bit */ + setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); +} +#endif void s_init(void) { @@ -113,6 +167,10 @@ void s_init(void) /* enable dumb pmic */ writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR); } + +#if defined(CONFIG_LDO_ENABLED_MODE) + init_ldo_mode(); +#endif return; }