From patchwork Thu Oct 6 10:23:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Avi Kivity X-Patchwork-Id: 118059 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AA5EFB6F94 for ; Thu, 6 Oct 2011 22:26:13 +1100 (EST) Received: from localhost ([::1]:40460 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RBl8R-0006Rs-Ag for incoming@patchwork.ozlabs.org; Thu, 06 Oct 2011 06:25:03 -0400 Received: from eggs.gnu.org ([140.186.70.92]:52251) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RBl7S-00046t-VS for qemu-devel@nongnu.org; Thu, 06 Oct 2011 06:24:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RBl7J-0002OX-6z for qemu-devel@nongnu.org; Thu, 06 Oct 2011 06:24:02 -0400 Received: from mx1.redhat.com ([209.132.183.28]:24611) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RBl7I-0002Nt-Hh for qemu-devel@nongnu.org; Thu, 06 Oct 2011 06:23:52 -0400 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p96ANp6i021647 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Thu, 6 Oct 2011 06:23:51 -0400 Received: from cleopatra.tlv.redhat.com (cleopatra.tlv.redhat.com [10.35.255.11]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id p96ANnbs031329 for ; Thu, 6 Oct 2011 06:23:50 -0400 Received: from s01.tlv.redhat.com (s01.tlv.redhat.com [10.35.255.8]) by cleopatra.tlv.redhat.com (Postfix) with ESMTP id E480B250B68; Thu, 6 Oct 2011 12:23:43 +0200 (IST) From: Avi Kivity To: qemu-devel@nongnu.org Date: Thu, 6 Oct 2011 12:23:16 +0200 Message-Id: <1317896615-25202-7-git-send-email-avi@redhat.com> In-Reply-To: <1317896615-25202-1-git-send-email-avi@redhat.com> References: <1317896615-25202-1-git-send-email-avi@redhat.com> X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 06/25] ppc405_boards: convert to memory API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Avi Kivity --- hw/ppc405_boards.c | 84 +++++++++++++++++++++++----------------------------- 1 files changed, 37 insertions(+), 47 deletions(-) diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index ca65ac3..b28bdda 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -137,16 +137,16 @@ static void ref405ep_fpga_writel (void *opaque, ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); } -static CPUReadMemoryFunc * const ref405ep_fpga_read[] = { - &ref405ep_fpga_readb, - &ref405ep_fpga_readw, - &ref405ep_fpga_readl, -}; - -static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = { - &ref405ep_fpga_writeb, - &ref405ep_fpga_writew, - &ref405ep_fpga_writel, +static const MemoryRegionOps ref405ep_fpga_ops = { + .old_mmio = { + .read = { + ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, + }, + .write = { + ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, + }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void ref405ep_fpga_reset (void *opaque) @@ -158,16 +158,15 @@ static void ref405ep_fpga_reset (void *opaque) fpga->reg1 = 0x0F; } -static void ref405ep_fpga_init (uint32_t base) +static void ref405ep_fpga_init (MemoryRegion *sysmem, uint32_t base) { ref405ep_fpga_t *fpga; - int fpga_memory; + MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); fpga = g_malloc0(sizeof(ref405ep_fpga_t)); - fpga_memory = cpu_register_io_memory(ref405ep_fpga_read, - ref405ep_fpga_write, fpga, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x00000100, fpga_memory); + memory_region_init_io(fpga_memory, &ref405ep_fpga_ops, fpga, + "fpga", 0x00000100); + memory_region_add_subregion(sysmem, base, fpga_memory); qemu_register_reset(&ref405ep_fpga_reset, fpga); } @@ -183,7 +182,8 @@ static void ref405ep_init (ram_addr_t ram_size, CPUPPCState *env; qemu_irq *pic; MemoryRegion *bios; - ram_addr_t sram_offset, bdloc; + MemoryRegion *sram = g_new(MemoryRegion, 1); + ram_addr_t bdloc; MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); target_phys_addr_t ram_bases[2], ram_sizes[2]; target_ulong sram_size; @@ -195,6 +195,7 @@ static void ref405ep_init (ram_addr_t ram_size, int linux_boot; int fl_idx, fl_sectors, len; DriveInfo *dinfo; + MemoryRegion *sysmem = get_system_memory(); /* XXX: fix this */ memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000); @@ -207,16 +208,12 @@ static void ref405ep_init (ram_addr_t ram_size, #ifdef DEBUG_BOARD_INIT printf("%s: register cpu\n", __func__); #endif - env = ppc405ep_init(get_system_memory(), ram_memories, ram_bases, ram_sizes, + env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 33333333, &pic, kernel_filename == NULL ? 0 : 1); /* allocate SRAM */ sram_size = 512 * 1024; - sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size); -#ifdef DEBUG_BOARD_INIT - printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset); -#endif - cpu_register_physical_memory(0xFFF00000, sram_size, - sram_offset | IO_MEM_RAM); + memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size); + memory_region_add_subregion(sysmem, 0xFFF00000, sram); /* allocate and load BIOS */ #ifdef DEBUG_BOARD_INIT printf("%s: register BIOS\n", __func__); @@ -263,14 +260,13 @@ static void ref405ep_init (ram_addr_t ram_size, } bios_size = (bios_size + 0xfff) & ~0xfff; memory_region_set_readonly(bios, true); - memory_region_add_subregion(get_system_memory(), - (uint32_t)(-bios_size), bios); + memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); } /* Register FPGA */ #ifdef DEBUG_BOARD_INIT printf("%s: register FPGA\n", __func__); #endif - ref405ep_fpga_init(0xF0300000); + ref405ep_fpga_init(sysmem, 0xF0300000); /* Register NVRAM */ #ifdef DEBUG_BOARD_INIT printf("%s: register NVRAM\n", __func__); @@ -468,16 +464,12 @@ static void taihu_cpld_writel (void *opaque, taihu_cpld_writeb(opaque, addr + 3, value & 0xFF); } -static CPUReadMemoryFunc * const taihu_cpld_read[] = { - &taihu_cpld_readb, - &taihu_cpld_readw, - &taihu_cpld_readl, -}; - -static CPUWriteMemoryFunc * const taihu_cpld_write[] = { - &taihu_cpld_writeb, - &taihu_cpld_writew, - &taihu_cpld_writel, +static const MemoryRegionOps taihu_cpld_ops = { + .old_mmio = { + .read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, }, + .write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void taihu_cpld_reset (void *opaque) @@ -489,16 +481,14 @@ static void taihu_cpld_reset (void *opaque) cpld->reg1 = 0x80; } -static void taihu_cpld_init (uint32_t base) +static void taihu_cpld_init (MemoryRegion *sysmem, uint32_t base) { taihu_cpld_t *cpld; - int cpld_memory; + MemoryRegion *cpld_memory = g_new(MemoryRegion, 1); cpld = g_malloc0(sizeof(taihu_cpld_t)); - cpld_memory = cpu_register_io_memory(taihu_cpld_read, - taihu_cpld_write, cpld, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x00000100, cpld_memory); + memory_region_init_io(cpld_memory, &taihu_cpld_ops, cpld, "cpld", 0x100); + memory_region_add_subregion(sysmem, base, cpld_memory); qemu_register_reset(&taihu_cpld_reset, cpld); } @@ -511,6 +501,7 @@ static void taihu_405ep_init(ram_addr_t ram_size, { char *filename; qemu_irq *pic; + MemoryRegion *sysmem = get_system_memory(); MemoryRegion *bios; MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); target_phys_addr_t ram_bases[2], ram_sizes[2]; @@ -534,7 +525,7 @@ static void taihu_405ep_init(ram_addr_t ram_size, #ifdef DEBUG_BOARD_INIT printf("%s: register cpu\n", __func__); #endif - ppc405ep_init(get_system_memory(), ram_memories, ram_bases, ram_sizes, + ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 33333333, &pic, kernel_filename == NULL ? 0 : 1); /* allocate and load BIOS */ #ifdef DEBUG_BOARD_INIT @@ -584,8 +575,7 @@ static void taihu_405ep_init(ram_addr_t ram_size, } bios_size = (bios_size + 0xfff) & ~0xfff; memory_region_set_readonly(bios, true); - memory_region_add_subregion(get_system_memory(), (uint32_t)(-bios_size), - bios); + memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); } /* Register Linux flash */ dinfo = drive_get(IF_PFLASH, 0, fl_idx); @@ -610,7 +600,7 @@ static void taihu_405ep_init(ram_addr_t ram_size, #ifdef DEBUG_BOARD_INIT printf("%s: register CPLD\n", __func__); #endif - taihu_cpld_init(0x50100000); + taihu_cpld_init(sysmem, 0x50100000); /* Load kernel */ linux_boot = (kernel_filename != NULL); if (linux_boot) {