On Mon, Oct 21, 2019 at 11:40 AM Simon Glass <sjg@chromium.org> wrote: > > For apollolake SPL is run from CAR (cache-as-RAM) which is in a different > location from where SPL must be placed in ROM. In other words, although > SPL runs before SDRAM is set up, it is not execute-in-place (XIP). > > Add a Kconfig option for the ROM position. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > Changes in v3: > - Add SPL condition to the option > > Changes in v2: None > > arch/x86/Kconfig | 5 +++++ > arch/x86/dts/u-boot.dtsi | 4 ++-- > 2 files changed, 7 insertions(+), 2 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f015e380f90..c9f1b6d8ada 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -914,4 +914,9 @@ config X86_OFFSET_U_BOOT depends on HAS_SYS_TEXT_BASE default SYS_TEXT_BASE +config X86_OFFSET_SPL + hex "Offset of SPL in ROM image" + depends on SPL && X86 + default SPL_TEXT_BASE + endmenu diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 66c4fdc8f8a..a8b57e78ead 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -45,7 +45,7 @@ }; #endif u-boot-spl { - offset = <CONFIG_SPL_TEXT_BASE>; + offset = <CONFIG_X86_OFFSET_SPL>; }; u-boot-spl-dtb { }; @@ -54,7 +54,7 @@ }; #elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { - offset = <CONFIG_SPL_TEXT_BASE>; + offset = <CONFIG_X86_OFFSET_SPL>; }; u-boot-dtb-with-ucode2 { type = "u-boot-dtb-with-ucode";
For apollolake SPL is run from CAR (cache-as-RAM) which is in a different location from where SPL must be placed in ROM. In other words, although SPL runs before SDRAM is set up, it is not execute-in-place (XIP). Add a Kconfig option for the ROM position. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v3: - Add SPL condition to the option Changes in v2: None arch/x86/Kconfig | 5 +++++ arch/x86/dts/u-boot.dtsi | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-)