From patchwork Mon Oct 21 03:39:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1180266 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="UDWS+M3A"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46xNfY6cc4z9sPL for ; Mon, 21 Oct 2019 15:18:13 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 90630C21DE8; Mon, 21 Oct 2019 03:52:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6AE08C21CB1; Mon, 21 Oct 2019 03:52:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A1690C21D83; Mon, 21 Oct 2019 03:40:55 +0000 (UTC) Received: from mail-io1-f66.google.com (mail-io1-f66.google.com [209.85.166.66]) by lists.denx.de (Postfix) with ESMTPS id 44A0EC21DEC for ; Mon, 21 Oct 2019 03:40:55 +0000 (UTC) Received: by mail-io1-f66.google.com with SMTP id p6so5956179iod.7 for ; Sun, 20 Oct 2019 20:40:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YDTsBWTQUCpvXw+tMzRn0FLebe0869RGFIXrQ8l//yk=; b=UDWS+M3AmjU6yao7egrDCNu86hsPofcx272ItTPxzt7DtHuNttahhYYRlbY6SYEc7z Rbcm+tnJIVTMuXJJyEM9283XeDBKPBkisE55B4L9UHSUUgTMJFhPgZBV6NAew3zIiZCN dIr9MQF2uAeGQhshkAWMaPHqWHxBCES7jsBHA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YDTsBWTQUCpvXw+tMzRn0FLebe0869RGFIXrQ8l//yk=; b=G1j37UufdiqYVKhlbY+yLbjhkE5ETiRsYteVRBV5TPex55CTmR9oTBnzg6F06e63Y/ u6p3SAut1KgYwFKT7Oe80mhwAFgeTKDUVksRS7oFhKMJUfHtE8tFepIOtebLtoSX0rOM KZklwjIjYSqZuHr+tPPWzus6m89OFNNgd4DNS3utiPdd8+p4isQqD4RduxP3wPXgtL5V QfVpnIuM4sePAyJFtaoq+bXBJaII6vvyioMfMFpRjDEzlpn67AnJXmcyxtazFcIQDQIN Mq5hPWv2n0cMwQTZ8wjJg7vxDWQXFN9ZdPOEgRH2hgIUc+kHV1EbSEJIrjMqLSOcl9by ikaA== X-Gm-Message-State: APjAAAWXD+NmkAJFHDE4QVda1Si2WAwGj0HhrOdQg7+ygImX7mqHYKPO zJbXxuOSYgUiUdII1SnEzd6cZx1lT77BLA== X-Google-Smtp-Source: APXvYqwWV+nV074F1fDS4AXcXInw4wjBp5T0eqjiUHM7QaaZaiI1BwIKIpSpxlAaRksRo7xVZayfRA== X-Received: by 2002:a6b:5104:: with SMTP id f4mr18942719iob.183.1571629254009; Sun, 20 Oct 2019 20:40:54 -0700 (PDT) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id x14sm1947028ion.67.2019.10.20.20.40.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2019 20:40:53 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Sun, 20 Oct 2019 21:39:05 -0600 Message-Id: <20191021033913.220758-95-sjg@chromium.org> X-Mailer: git-send-email 2.23.0.866.gb869b98d4c-goog In-Reply-To: <20191021033913.220758-22-sjg@chromium.org> References: <20191021033913.220758-22-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v3 100/108] x86: apollolake: Add PUNIT driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a driver for the apollolake power unit. It is modelled as a syscon driver since it only needs to be probed. Signed-off-by: Simon Glass --- Changes in v3: - Use pci_get_devfn() Changes in v2: None arch/x86/cpu/apollolake/Makefile | 3 + arch/x86/cpu/apollolake/punit.c | 121 +++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 arch/x86/cpu/apollolake/punit.c diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 7f76572e551..8a177d93d00 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -3,6 +3,9 @@ # Copyright (c) 2016 Google, Inc obj-$(CONFIG_SPL_BUILD) += systemagent.o +ifndef CONFIG_TPL_BUILD +obj-y += punit.o +endif obj-y += gpio.o obj-y += hostbridge.o diff --git a/arch/x86/cpu/apollolake/punit.c b/arch/x86/cpu/apollolake/punit.c new file mode 100644 index 00000000000..c8e55a24d8a --- /dev/null +++ b/arch/x86/cpu/apollolake/punit.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * struct apl_punit_platdata - platform data for punit + * + * @pciex_region_size: BAR length in bytes + */ +struct apl_punit_platdata { + pci_dev_t bdf; +}; + +/* + * Punit Initialization code. This all isn't documented, but + * this is the recipe. + */ +static int punit_init(struct udevice *dev) +{ + struct apl_punit_platdata *plat = dev_get_platdata(dev); + struct udevice *cpu; + u32 reg; + ulong start; + int ret; + + /* Thermal throttle activation offset */ + ret = uclass_first_device_err(UCLASS_CPU, &cpu); + if (ret) + return log_msg_ret("Cannot find CPU", ret); + cpu_configure_thermal_target(cpu); + + /* + * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). + * Enable all cores here. + */ + writel(0, MCHBAR_REG(CORE_DISABLE_MASK)); + + /* P-Unit bring up */ + reg = readl(MCHBAR_REG(BIOS_RESET_CPL)); + if (reg == 0xffffffff) { + /* P-unit not found */ + debug("Punit MMIO not available\n"); + return -ENOENT; + } + + /* Set Punit interrupt pin IPIN offset 3D */ + pci_x86_write_config(plat->bdf, PCI_INTERRUPT_PIN, 0x2, PCI_SIZE_8); + + /* Set PUINT IRQ to 24 and INTPIN LOCK */ + writel(PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | + PUINT_THERMAL_DEVICE_IRQ_LOCK, + MCHBAR_REG(PUNIT_THERMAL_DEVICE_IRQ)); + + if (!IS_ENABLED(SOC_INTEL_GLK)) + clrsetbits_le32(MCHBAR_REG(0x7818), 0x1fe0, 0x220); + + /* Stage0 BIOS Reset Complete (RST_CPL) */ + enable_bios_reset_cpl(); + + /* + * Poll for bit 8 to check if PCODE has completed its action in response + * to BIOS Reset complete. We wait here till 1 ms for the bit to get + * set. + */ + start = get_timer(0); + while (!(readl(MCHBAR_REG(BIOS_RESET_CPL)) & PCODE_INIT_DONE)) { + if (get_timer(start) > 1) { + debug("PCODE Init Done timeout\n"); + return -ETIMEDOUT; + } + udelay(100); + } + debug("PUNIT init complete\n"); + + return 0; +} + +static int apl_punit_probe(struct udevice *dev) +{ + if (spl_phase() == PHASE_SPL) + return punit_init(dev); + + return 0; +} + +static int apl_punit_ofdata_to_platdata(struct udevice *dev) +{ + struct apl_punit_platdata *plat = dev_get_platdata(dev); + int root; + + root = pci_get_devfn(dev); + if (root < 0) + return log_msg_ret("Cannot get host-bridge PCI address", root); + plat->bdf = root; + + return 0; +} + +static const struct udevice_id apl_syscon_ids[] = { + { .compatible = "intel,apl-punit", .data = X86_SYSCON_PUNIT }, + { } +}; + +U_BOOT_DRIVER(syscon_intel_punit) = { + .name = "intel_punit_syscon", + .id = UCLASS_SYSCON, + .of_match = apl_syscon_ids, + .ofdata_to_platdata = apl_punit_ofdata_to_platdata, + .probe = apl_punit_probe, +};