From patchwork Mon Oct 21 03:39:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1180202 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="aOcdKTXW"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46xMy14GcNz9sPL for ; Mon, 21 Oct 2019 14:46:32 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id F25E7C21DD4; Mon, 21 Oct 2019 03:41:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 48BF8C21E0B; Mon, 21 Oct 2019 03:41:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CA9D2C21DEC; Mon, 21 Oct 2019 03:40:56 +0000 (UTC) Received: from mail-io1-f65.google.com (mail-io1-f65.google.com [209.85.166.65]) by lists.denx.de (Postfix) with ESMTPS id 1A8F9C21DD7 for ; Mon, 21 Oct 2019 03:40:56 +0000 (UTC) Received: by mail-io1-f65.google.com with SMTP id r144so2310543iod.8 for ; Sun, 20 Oct 2019 20:40:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O/XWcnWD1cdDCCcQzReWNX5TvN9zm7bD7IcNWJeUJbI=; b=aOcdKTXWE3WdtBgV40HG3eijSNtJSlgNJUD1/WeFpFoouLSdPy3xhajE+mPR2FrdPP yvqnNeuAeB0A4RSz3m6rchWwTSBr8IfeB+fGqfFktq3rZwod8WuI9L6nkfwR8eRjfB74 XVA6HO9+iNgCe8nsRThdsJzDKx8KUJ2tU98ZI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O/XWcnWD1cdDCCcQzReWNX5TvN9zm7bD7IcNWJeUJbI=; b=RLvWk4o7qNEZriMHyMiZ/XteFJ2uKl4kE8bTPlAE/CX7ThMfEoUtPJPWC+uu9CYIrC CYrIf5lHuC/xRjXkBdWTipO/Bt+ygsBxe+lZ7gOrAl52e3RSLTubHSMZLPtEOEIqVC9n F6JlWVpV7ADY0v4NH4QErIFj+4Kwf3KLNqKLaFN+uF0pkO2G9OQUTr0V1rtwOvXXm743 04YlBFA+9T1jd219xTjGPEyZGJuMNf8jhktPIRYXTyaIGU6yKeJQgjDtmcMm0yE4opo/ KzQsE8R0Q9FFExZeq/fFmAwHVLWMPF56Bau36Sj6ySoGiFKARJYba+OIBi52m4lK9u9d rzaA== X-Gm-Message-State: APjAAAXHIVTiZ0SeVRdvuZ0VahxV+C/7B3S9VsZkgk2FlZ0mxuLTF+Ej B9GIeccjhNV92xdlCLRykhCx7GvjhuH5Zg== X-Google-Smtp-Source: APXvYqxwx3FHmDD3yzsxWae9Kptf/W9KSSMXm+28Ld5wuPVYChGvqdhTJhWq099IEM2GmkR2UXn6qg== X-Received: by 2002:a5d:8d13:: with SMTP id p19mr19216784ioj.306.1571629254726; Sun, 20 Oct 2019 20:40:54 -0700 (PDT) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id x14sm1947028ion.67.2019.10.20.20.40.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2019 20:40:54 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Sun, 20 Oct 2019 21:39:06 -0600 Message-Id: <20191021033913.220758-96-sjg@chromium.org> X-Mailer: git-send-email 2.23.0.866.gb869b98d4c-goog In-Reply-To: <20191021033913.220758-22-sjg@chromium.org> References: <20191021033913.220758-22-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v3 101/108] x86: apollolake: Add SPL loaders X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add loaders for SPL and TPL so that the next stage can be loaded from memory-mapped SPI or, failing that, the Fast SPI driver. Signed-off-by: Simon Glass --- Changes in v3: - Add a driver for APL SPI for TPL (using of-platdata) - Support TPL without CONFIG_TPL_SPI_SUPPORT - Support bootstage timing Changes in v2: None arch/x86/cpu/apollolake/Makefile | 2 + arch/x86/cpu/apollolake/spl.c | 202 +++++++++++++++++++++++++++++++ 2 files changed, 204 insertions(+) create mode 100644 arch/x86/cpu/apollolake/spl.c diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 8a177d93d00..c4ec71e2b76 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -2,7 +2,9 @@ # # Copyright (c) 2016 Google, Inc +obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += systemagent.o + ifndef CONFIG_TPL_BUILD obj-y += punit.o endif diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c new file mode 100644 index 00000000000..a12379e312d --- /dev/null +++ b/arch/x86/cpu/apollolake/spl.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * We need to read well past the end of the region in order for execution from + * the loaded data to work. It is not clear why. + */ +#define SAFETY_MARGIN 0x4000 + +binman_sym_declare(ulong, u_boot_spl, image_pos); +binman_sym_declare(ulong, u_boot_spl, size); +/* U-Boot image_pos is declared by common/spl/spl.c */ +binman_sym_declare(ulong, u_boot_any, size); + +static ulong get_image_pos(void) +{ + return spl_phase() == PHASE_TPL ? + binman_sym(ulong, u_boot_spl, image_pos) : + binman_sym(ulong, u_boot_any, image_pos); +} + +static ulong get_image_size(void) +{ + return spl_phase() == PHASE_TPL ? + binman_sym(ulong, u_boot_spl, size) : + binman_sym(ulong, u_boot_any, size); +} + +/* This reads the next phase from mapped SPI flash */ +static int rom_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + ulong spl_pos = get_image_pos(); + ulong spl_size = get_image_size(); + struct udevice *dev; + ulong map_base; + size_t map_size; + uint offset; + int ret; + + spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */ + spl_image->entry_point = spl_phase() == PHASE_TPL ? + CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE; + spl_image->load_addr = spl_image->entry_point; + spl_image->os = IH_OS_U_BOOT; + spl_image->name = "U-Boot"; + debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size); + + if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) { + ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev); + if (ret) + return log_msg_ret("spi_flash", ret); + if (!dev) + return log_msg_ret("spi_flash dev", -ENODEV); + ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset); + if (ret) + return log_msg_ret("mmap", ret); + } else { + ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size, + &offset); + if (ret) + return ret; + } + spl_pos += map_base & ~0xff000000; + debug(", base %lx, pos %lx\n", map_base, spl_pos); + bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi"); + memcpy((void *)spl_image->load_addr, (void *)spl_pos, + spl_size + SAFETY_MARGIN); + bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI); + + return 0; +} +SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image); + +#if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT) + +static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len, + void *buf) +{ + struct spi_flash *flash = dev_get_uclass_priv(dev); + struct mtd_info *mtd = &flash->mtd; + size_t retlen; + + return log_ret(mtd->_read(mtd, offset, len, &retlen, buf)); +} + +static int apl_flash_probe(struct udevice *dev) +{ + return spi_flash_std_probe(dev); +} + +/* + * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also + * need to allocate the parent_platdata since by the time this function is + * called device_bind() has already gone past that step. + */ +static int apl_flash_bind(struct udevice *dev) +{ + if (CONFIG_IS_ENABLED(OF_PLATDATA)) { + struct dm_spi_slave_platdata *plat; + struct udevice *spi; + int ret; + + ret = uclass_first_device_err(UCLASS_SPI, &spi); + if (ret) + return ret; + dev->parent = spi; + + plat = calloc(sizeof(*plat), 1); + if (!plat) + return -ENOMEM; + dev->parent_platdata = plat; + } + + return 0; +} + +static const struct dm_spi_flash_ops apl_flash_ops = { + .read = apl_flash_std_read, +}; + +static const struct udevice_id apl_flash_ids[] = { + { .compatible = "jedec,spi-nor" }, + { } +}; + +U_BOOT_DRIVER(winbond_w25q128fw) = { + .name = "winbond_w25q128fw", + .id = UCLASS_SPI_FLASH, + .of_match = apl_flash_ids, + .bind = apl_flash_bind, + .probe = apl_flash_probe, + .priv_auto_alloc_size = sizeof(struct spi_flash), + .ops = &apl_flash_ops, +}; + +/* This uses a SPI flash device to read the next phase */ +static int spl_fast_spi_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + ulong spl_pos = get_image_pos(); + ulong spl_size = get_image_size(); + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev); + if (ret) + return ret; + + spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */ + spl_image->entry_point = spl_phase() == PHASE_TPL ? + CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE; + spl_image->load_addr = spl_image->entry_point; + spl_image->os = IH_OS_U_BOOT; + spl_image->name = "U-Boot"; + spl_pos &= ~0xff000000; + debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size); + ret = spi_flash_read_dm(dev, spl_pos, spl_size + SAFETY_MARGIN, + (void *)spl_image->load_addr); + if (ret) + return ret; + + return 0; +} +SPL_LOAD_IMAGE_METHOD("Fast SPI", 1, BOOT_DEVICE_FAST_SPI, + spl_fast_spi_load_image); + +void board_boot_order(u32 *spl_boot_list) +{ + bool use_spi_flash = BOOT_FROM_FAST_SPI_FLASH; + + if (use_spi_flash) { + spl_boot_list[0] = BOOT_DEVICE_FAST_SPI; + spl_boot_list[1] = BOOT_DEVICE_SPI_MMAP; + } else { + spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP; + spl_boot_list[1] = BOOT_DEVICE_FAST_SPI; + } +} + +#else + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP; +} +#endif