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[92.34.200.121]) by smtp.gmail.com with ESMTPSA id 77sm6011174ljf.85.2019.10.20.16.00.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2019 16:00:45 -0700 (PDT) From: Linus Walleij To: David Woodhouse , Brian Norris , Marek Vasut , Richard Weinberger , Miquel Raynal , Vignesh Raghavendra Cc: linux-mtd@lists.infradead.org, Linus Walleij , devicetree@vger.kernel.org, Rob Herring Subject: [PATCH 1/2 v4] mtd: add DT bindings for the Intel IXP4xx Flash Date: Mon, 21 Oct 2019 01:00:41 +0200 Message-Id: <20191020230042.7364-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Intel IXP4xx flash controller, a simple physmap which however need a specific big-endian or mixed-endian access pattern to the memory. Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - Rebase on v5.4-rc1 - Resend ChangeLog v2->v3: - Rebase on v5.1-rc1 - Resend ChangeLog v1->v2: - Collect Rob's Review tag. --- .../bindings/mtd/intel,ixp4xx-flash.txt | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt diff --git a/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt b/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt new file mode 100644 index 000000000000..4bdcb92ae381 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt @@ -0,0 +1,22 @@ +Flash device on Intel IXP4xx SoC + +This flash is regular CFI compatible (Intel or AMD extended) flash chips with +specific big-endian or mixed-endian memory access pattern. + +Required properties: +- compatible : must be "intel,ixp4xx-flash", "cfi-flash"; +- reg : memory address for the flash chip +- bank-width : width in bytes of flash interface, should be <2> + +For the rest of the properties, see mtd-physmap.txt. + +The device tree may optionally contain sub-nodes describing partitions of the +address space. See partition.txt for more detail. + +Example: + +flash@50000000 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + reg = <0x50000000 0x01000000>; + bank-width = <2>; +};