From patchwork Fri Oct 18 19:48:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw (lists)" X-Patchwork-Id: 1179647 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-511335-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="JcXkLH7F"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46vxhl2WcKz9sP7 for ; Sat, 19 Oct 2019 07:00:07 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=yhmsjhuftypndt4l vokJUlHLTavbZSXyOYG4ZinC9Wa7SPmD6s6NE2r3rvaiZzPIVBWDhQ1UjsjkFKC5 bDtoUkfVuU7bBZ9PT7V3IK2BJlJZ2tC+/+939zYQOFgeJOR/z0gFpaAFpMbP4F3U qeRB5wGPGlGfUZPi/PAUJ3AFfhE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=9HtAt3H0whpp46X8SZQ6ht LNzuc=; b=JcXkLH7Fk1ua8AaRW6sZq8JUsXFRV0WWTrie/c9dFub66dyOvJEOZf FmMZYvewmjqY5KVX3mzBCz8IPrc06umglb2Bah6r90FUpGDkjXOdAmz1i3J02tHR D3MwyWysQI3X2Cl4WoLqaz3yNa9siQeQlWF5l2h6Ws3mhip0Snzyk= Received: (qmail 121868 invoked by alias); 18 Oct 2019 19:56:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 115904 invoked by uid 89); 18 Oct 2019 19:55:51 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, SPF_FAIL autolearn=ham version=3.3.1 spammy=rework X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (209.51.188.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 18 Oct 2019 19:55:47 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iLYLd-0005AO-50 for gcc-patches@gcc.gnu.org; Fri, 18 Oct 2019 15:55:42 -0400 Received: from [217.140.110.172] (port=42752 helo=foss.arm.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1iLYLc-00054V-Sn for gcc-patches@gcc.gnu.org; Fri, 18 Oct 2019 15:55:41 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7D0661758; Fri, 18 Oct 2019 12:49:25 -0700 (PDT) Received: from eagle.buzzard.freeserve.co.uk (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0A8893F6C4; Fri, 18 Oct 2019 12:49:24 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 19/29] [arm] Handle immediate values in uaddvsi4 Date: Fri, 18 Oct 2019 20:48:50 +0100 Message-Id: <20191018194900.34795-20-Richard.Earnshaw@arm.com> In-Reply-To: <20191018194900.34795-1-Richard.Earnshaw@arm.com> References: <20191018194900.34795-1-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.110.172 The uaddv patterns in the arm back-end do not currenty handle immediates during expansion. This patch adds this support for uaddvsi4. It's really a stepping-stone towards early expansion of uaddvdi4, but it complete and a useful change in its own right. Whilst making this change I also observed that we really had two patterns that did exactly the same thing, but with slightly different properties; consequently I've cleaned up all of the add-and-compare patterns to bring some consistency. * config/arm/arm.md (adddi3): Call gen_addsi3_compare_op1. * (uaddv4): Delete expansion pattern. (uaddvsi4): New pattern. (uaddvdi4): Likewise. (addsi3_compareC): Delete pattern, change callers to use addsi3_compare_op1. (addsi3_compare_op1): No-longer anonymous. Clean up constraints to reduce the number of alternatives and re-work type attribute handling. (addsi3_compare_op2): Clean up constraints to reduce the number of alternatives and re-work type attribute handling. (compare_addsi2_op0): Likewise. (compare_addsi2_op1): Likewise. --- gcc/config/arm/arm.md | 118 ++++++++++++++++++++++-------------------- 1 file changed, 62 insertions(+), 56 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index eaadfd64128..4ea6f4b226c 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -470,7 +470,7 @@ (define_expand "adddi3" if (!arm_not_operand (hi_op2, SImode)) hi_op2 = force_reg (SImode, hi_op2); - emit_insn (gen_addsi3_compareC (lo_dest, lo_op1, lo_op2)); + emit_insn (gen_addsi3_compare_op1 (lo_dest, lo_op1, lo_op2)); rtx carry = gen_rtx_LTU (SImode, gen_rtx_REG (CC_Cmode, CC_REGNUM), const0_rtx); if (hi_op2 == const0_rtx) @@ -501,14 +501,27 @@ (define_expand "addv4" DONE; }) -(define_expand "uaddv4" - [(match_operand:SIDI 0 "register_operand") - (match_operand:SIDI 1 "register_operand") - (match_operand:SIDI 2 "register_operand") +(define_expand "uaddvsi4" + [(match_operand:SI 0 "s_register_operand") + (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "arm_add_operand") (match_operand 3 "")] "TARGET_32BIT" { - emit_insn (gen_add3_compareC (operands[0], operands[1], operands[2])); + emit_insn (gen_addsi3_compare_op1 (operands[0], operands[1], operands[2])); + arm_gen_unlikely_cbranch (LTU, CC_Cmode, operands[3]); + + DONE; +}) + +(define_expand "uaddvdi4" + [(match_operand:DI 0 "s_register_operand") + (match_operand:DI 1 "s_register_operand") + (match_operand:DI 2 "s_register_operand") + (match_operand 3 "")] + "TARGET_32BIT" +{ + emit_insn (gen_adddi3_compareC (operands[0], operands[1], operands[2])); arm_gen_unlikely_cbranch (LTU, CC_Cmode, operands[3]); DONE; @@ -639,19 +652,6 @@ (define_insn "adddi3_compareC" (set_attr "type" "multiple")] ) -(define_insn "addsi3_compareC" - [(set (reg:CC_C CC_REGNUM) - (compare:CC_C (plus:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "register_operand" "r")) - (match_dup 1))) - (set (match_operand:SI 0 "register_operand" "=r") - (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT" - "adds%?\\t%0, %1, %2" - [(set_attr "conds" "set") - (set_attr "type" "alus_sreg")] -) - (define_insn "addsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV @@ -770,13 +770,13 @@ (define_peephole2 ;; the operands, and we know that the use of the condition code is ;; either GEU or LTU, so we can use the carry flag from the addition ;; instead of doing the compare a second time. -(define_insn "*addsi3_compare_op1" +(define_insn "addsi3_compare_op1" [(set (reg:CC_C CC_REGNUM) (compare:CC_C - (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,r,r,r") - (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,I,L,r")) + (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,rk,rk") + (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,rkI,L")) (match_dup 1))) - (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r,r") + (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,rk,rk") (plus:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "@ @@ -785,22 +785,23 @@ (define_insn "*addsi3_compare_op1" subs%?\\t%0, %1, #%n2 subs%?\\t%0, %0, #%n2 adds%?\\t%0, %1, %2 - subs%?\\t%0, %1, #%n2 - adds%?\\t%0, %1, %2" + subs%?\\t%0, %1, #%n2" [(set_attr "conds" "set") - (set_attr "arch" "t2,t2,t2,t2,*,*,*") - (set_attr "length" "2,2,2,2,4,4,4") - (set_attr "type" - "alus_sreg,alus_imm,alus_sreg,alus_imm,alus_imm,alus_imm,alus_sreg")] + (set_attr "arch" "t2,t2,t2,t2,*,*") + (set_attr "length" "2,2,2,2,4,4") + (set (attr "type") + (if_then_else (match_operand 2 "const_int_operand") + (const_string "alu_imm") + (const_string "alu_sreg")))] ) (define_insn "*addsi3_compare_op2" [(set (reg:CC_C CC_REGNUM) (compare:CC_C - (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,r,r,r") - (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,I,L,r")) + (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,r,r") + (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,rI,L")) (match_dup 2))) - (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r,r") + (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r") (plus:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "@ @@ -809,55 +810,60 @@ (define_insn "*addsi3_compare_op2" subs%?\\t%0, %1, #%n2 subs%?\\t%0, %0, #%n2 adds%?\\t%0, %1, %2 - subs%?\\t%0, %1, #%n2 - adds%?\\t%0, %1, %2" + subs%?\\t%0, %1, #%n2" [(set_attr "conds" "set") - (set_attr "arch" "t2,t2,t2,t2,*,*,*") - (set_attr "length" "2,2,2,2,4,4,4") - (set_attr "type" - "alus_sreg,alus_imm,alus_sreg,alus_imm,alus_imm,alus_imm,alus_sreg")] + (set_attr "arch" "t2,t2,t2,t2,*,*") + (set_attr "length" "2,2,2,2,4,4") + (set (attr "type") + (if_then_else (match_operand 2 "const_int_operand") + (const_string "alu_imm") + (const_string "alu_sreg")))] ) (define_insn "*compare_addsi2_op0" [(set (reg:CC_C CC_REGNUM) (compare:CC_C - (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r") - (match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r")) + (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r") + (match_operand:SI 1 "arm_add_operand" "l,Pw,rI,L")) (match_dup 0)))] "TARGET_32BIT" "@ - cmp%?\\t%0, #%n1 - cmn%?\\t%0, %1 cmn%?\\t%0, %1 cmp%?\\t%0, #%n1 - cmn%?\\t%0, %1" + cmn%?\\t%0, %1 + cmp%?\\t%0, #%n1" [(set_attr "conds" "set") (set_attr "predicable" "yes") - (set_attr "arch" "t2,t2,*,*,*") - (set_attr "predicable_short_it" "yes,yes,no,no,no") - (set_attr "length" "2,2,4,4,4") - (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")] + (set_attr "arch" "t2,t2,*,*") + (set_attr "predicable_short_it" "yes,yes,no,no") + (set_attr "length" "2,2,4,4") + (set (attr "type") + (if_then_else (match_operand 1 "const_int_operand") + (const_string "alu_imm") + (const_string "alu_sreg")))] ) (define_insn "*compare_addsi2_op1" [(set (reg:CC_C CC_REGNUM) (compare:CC_C - (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r") - (match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r")) + (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r") + (match_operand:SI 1 "arm_add_operand" "l,Pw,rI,L")) (match_dup 1)))] "TARGET_32BIT" "@ - cmp%?\\t%0, #%n1 - cmn%?\\t%0, %1 cmn%?\\t%0, %1 cmp%?\\t%0, #%n1 - cmn%?\\t%0, %1" + cmn%?\\t%0, %1 + cmp%?\\t%0, #%n1" [(set_attr "conds" "set") (set_attr "predicable" "yes") - (set_attr "arch" "t2,t2,*,*,*") - (set_attr "predicable_short_it" "yes,yes,no,no,no") - (set_attr "length" "2,2,4,4,4") - (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")] + (set_attr "arch" "t2,t2,*,*") + (set_attr "predicable_short_it" "yes,yes,no,no") + (set_attr "length" "2,2,4,4") + (set (attr "type") + (if_then_else (match_operand 1 "const_int_operand") + (const_string "alu_imm") + (const_string "alu_sreg")))] ) (define_insn "addsi3_carryin"