From patchwork Fri Oct 18 19:48:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw (lists)" X-Patchwork-Id: 1179633 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-511321-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="PBDi5aLl"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46vxdD6BFzz9sP7 for ; Sat, 19 Oct 2019 06:57:03 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=aKj6qFQSyMdMcr8q P9H9pzOI2XJ9/hKhNB8p7c2zKlwAz7c6o1iKmph3NppuNmvoc7ooqntJm3Ql8uEr u8Qb40GA5Pnza9bMABknUR5qGq/pH48Rn82dtBi0NwVW63HUoX3ueoo59fIP4fG+ OM0xLqST4A6mV6JsQPBIVkXxbJM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=OQLRzcMh/sM7YRMrj38x7p de7B0=; b=PBDi5aLloQZziVyKeC/KDKMsLkjI5At7+asSAKA1aG98ymtyOT5yLG n3tmDfoWPHMX0MbUDnZn1JCib7lmr1ff8WwehGD2hFR9zM0NTwU6HCoAOdc2oEcS y+YGAAgnKdxILAgSL2gjjE5/1xpu6RE6NouscVHmKNZXt3tKHPF1M= Received: (qmail 113622 invoked by alias); 18 Oct 2019 19:55:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 110798 invoked by uid 89); 18 Oct 2019 19:55:37 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_FAIL autolearn=ham version=3.3.1 spammy=practically, REG_DEAD, reg_dead, disappear X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (209.51.188.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 18 Oct 2019 19:55:34 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iLYLR-00054R-Ti for gcc-patches@gcc.gnu.org; Fri, 18 Oct 2019 15:55:31 -0400 Received: from [217.140.110.172] (port=42746 helo=foss.arm.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1iLYLR-000549-LH for gcc-patches@gcc.gnu.org; Fri, 18 Oct 2019 15:55:29 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 026DD1692; Fri, 18 Oct 2019 12:49:20 -0700 (PDT) Received: from eagle.buzzard.freeserve.co.uk (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 83C123F6C4; Fri, 18 Oct 2019 12:49:19 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 11/29] [arm] Reduce cost of insns that are simple reg-reg moves. Date: Fri, 18 Oct 2019 20:48:42 +0100 Message-Id: <20191018194900.34795-12-Richard.Earnshaw@arm.com> In-Reply-To: <20191018194900.34795-1-Richard.Earnshaw@arm.com> References: <20191018194900.34795-1-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.110.172 Consider this sequence during combine: Trying 18, 7 -> 22: 18: r118:SI=r122:SI REG_DEAD r122:SI 7: r114:SI=0x1-r118:SI-ltu(cc:CC_RSB,0) REG_DEAD r118:SI REG_DEAD cc:CC_RSB 22: r1:SI=r114:SI REG_DEAD r114:SI Failed to match this instruction: (set (reg:SI 1 r1 [+4 ]) (minus:SI (geu:SI (reg:CC_RSB 100 cc) (const_int 0 [0])) (reg:SI 122))) Successfully matched this instruction: (set (reg:SI 114) (geu:SI (reg:CC_RSB 100 cc) (const_int 0 [0]))) Successfully matched this instruction: (set (reg:SI 1 r1 [+4 ]) (minus:SI (reg:SI 114) (reg:SI 122))) allowing combination of insns 18, 7 and 22 original costs 4 + 4 + 4 = 12 replacement costs 8 + 4 = 12 The costs are all correct, but we really don't want this combination to take place. The original costs contain an insn that is a simple move of one pseudo register to another and it is extremely likely that register allocation will eliminate this insn entirely. On the other hand, the resulting sequence really does expand into a sequence that costs 12 (ie 3 insns). We don't want to prevent combine from eliminating such moves, as this can expose more combine opportunities, but we shouldn't rate them as profitable in themselves. We can do this be adjusting the costs slightly so that the benefit of eliminating such a simple insn is reduced. We only do this before register allocation; after allocation we give such insns their full cost. * config/arm/arm.c (arm_insn_cost): New function. (TARGET_INSN_COST): Override default definition. --- gcc/config/arm/arm.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index b91b52f6d51..e33b6b14d28 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -181,6 +181,7 @@ static bool arm_have_conditional_execution (void); static bool arm_cannot_force_const_mem (machine_mode, rtx); static bool arm_legitimate_constant_p (machine_mode, rtx); static bool arm_rtx_costs (rtx, machine_mode, int, int, int *, bool); +static int arm_insn_cost (rtx_insn *, bool); static int arm_address_cost (rtx, machine_mode, addr_space_t, bool); static int arm_register_move_cost (machine_mode, reg_class_t, reg_class_t); static int arm_memory_move_cost (machine_mode, reg_class_t, bool); @@ -510,6 +511,8 @@ static const struct attribute_spec arm_attribute_table[] = #define TARGET_RTX_COSTS arm_rtx_costs #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST arm_address_cost +#undef TARGET_INSN_COST +#define TARGET_INSN_COST arm_insn_cost #undef TARGET_SHIFT_TRUNCATION_MASK #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask @@ -11486,6 +11489,24 @@ arm_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, return result; } +static int +arm_insn_cost (rtx_insn *insn, bool speed) +{ + int cost; + + /* Don't cost a simple reg-reg move at a full insn cost: such moves + will likely disappear during register allocation. */ + if (!reload_completed + && GET_CODE (PATTERN (insn)) == SET + && REG_P (SET_DEST (PATTERN (insn))) + && REG_P (SET_SRC (PATTERN (insn)))) + return 2; + cost = pattern_cost (PATTERN (insn), speed); + /* If the cost is zero, then it's likely a complex insn. We don't want the + cost of these to be less than something we know about. */ + return cost ? cost : COSTS_N_INSNS (2); +} + /* All address computations that can be done are free, but rtx cost returns the same for practically all of them. So we weight the different types of address here in the order (most pref first):