| Message ID | 20191017092144.19525-5-laurentiu.tudor@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | Priyanka Jain |
| Headers | show |
| Series | [U-Boot,1/6] armv8: fsl-layerscape: guard caam specific defines | expand |
>-----Original Message----- >From: u-boot-bounces@linux.nxdi.nxp.com <u-boot- >bounces@linux.nxdi.nxp.com> On Behalf Of Laurentiu Tudor >Sent: Thursday, October 17, 2019 2:52 PM >To: u-boot@lists.denx.de; Prabhakar X <prabhakar.kushwaha@nxp.com> >Subject: [u-boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform >devices > >From: Laurentiu Tudor <laurentiu.tudor@nxp.com> > >Add ICID setup for the platform devices contained on this chip: usb, sata, >sdhc, sec. > >Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> >--- > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + > .../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++++++++++++++++++ > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- > .../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +- > .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 + > board/freescale/lx2160a/lx2160a.c | 2 + > include/fsl_sec.h | 3 +- > 7 files changed, 58 insertions(+), 4 deletions(-) create mode 100644 >arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c > >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile >b/arch/arm/cpu/armv8/fsl-layerscape/Makefile >index f00ef817b1..e398aecd12 100644 >--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile >+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile >@@ -24,6 +24,7 @@ endif > > ifneq ($(CONFIG_ARCH_LX2160A),) > obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o >+obj-y += icid.o lx2160_ids.o > endif > > ifneq ($(CONFIG_ARCH_LS2080A),) >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >new file mode 100644 >index 0000000000..3a0ed1fa55 >--- /dev/null >+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >@@ -0,0 +1,48 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+/* >+ * Copyright 2019 NXP >+ */ >+ >+#include <common.h> >+#include <asm/arch-fsl-layerscape/immap_lsch3.h> >+#include <asm/arch-fsl-layerscape/fsl_icid.h> >+#include <asm/arch-fsl-layerscape/fsl_portals.h> >+ >+struct icid_id_table icid_tbl[] = { >+ SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), >+ SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID), >+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), >+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), >+ SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID), >+ SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID), >+ SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID), >+ SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID), #ifdef >+CONFIG_FSL_CAAM >+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), >+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), >+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), >+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), >+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), >+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), >+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), >+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID), #endif }; >+ >+int icid_tbl_sz = ARRAY_SIZE(icid_tbl); >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c >b/arch/arm/cpu/armv8/fsl-layerscape/soc.c >index 924f5f3fe8..4dea8361fc 100644 >--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c >+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c >@@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void) #endif > > #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ >- defined(CONFIG_ARCH_LS2080A) >+ defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) > set_icids(); > #endif > } >diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >index 0e4bf331fd..f86835a33d 100644 >--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >@@ -447,7 +447,9 @@ struct ccsr_gur { > u8 res_538[0x550 - 0x538]; /* add more registers when needed */ > u32 sata1_amqr; > u32 sata2_amqr; >- u8 res_558[0x570-0x558]; /* add more registers when needed */ >+ u32 sata3_amqr; >+ u32 sata4_amqr; >+ u8 res_558[0x570 - 0x560]; /* add more registers when needed */ This will change the byte position for below variables. Please confirm that you have cross-checked and tested this update for all lsch3 SoC > u32 misc1_amqr; > u8 res_574[0x590-0x574]; /* add more registers when needed */ > u32 spare1_amqr; >diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h >b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h >index 93bdcc4caa..0b36416ad3 100644 >--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h >+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h >@@ -108,5 +108,7 @@ > #define FSL_EDMA_STREAM_ID 70 > #define FSL_GPU_STREAM_ID 71 > #define FSL_DISPLAY_STREAM_ID 72 >+#define FSL_SATA3_STREAM_ID 73 >+#define FSL_SATA4_STREAM_ID 74 > > #endif >diff --git a/board/freescale/lx2160a/lx2160a.c >b/board/freescale/lx2160a/lx2160a.c >index b509c0312e..eff12747b4 100644 >--- a/board/freescale/lx2160a/lx2160a.c >+++ b/board/freescale/lx2160a/lx2160a.c >@@ -27,6 +27,7 @@ > #include "../common/qixis.h" > #include "../common/vid.h" > #include <fsl_immap.h> >+#include <asm/arch-fsl-layerscape/fsl_icid.h> > > #ifdef CONFIG_EMC2305 > #include "../common/emc2305.h" >@@ -684,6 +685,7 @@ int ft_board_setup(void *blob, bd_t *bd) > fdt_fsl_mc_fixup_iommu_map_entry(blob); > fdt_fixup_board_enet(blob); > #endif >+ fdt_fixup_icid(blob); > > return 0; > } >diff --git a/include/fsl_sec.h b/include/fsl_sec.h index >be08a2b88b..c0d2c7e866 100644 >--- a/include/fsl_sec.h >+++ b/include/fsl_sec.h >@@ -93,8 +93,7 @@ typedef struct ccsr_sec { > struct { > u32 ms; /* DECO LIODN Register, MS */ > u32 ls; /* DECO LIODN Register, LS */ >- } decoliodnr[8]; >- u8 res4[0x40]; >+ } decoliodnr[16]; > u32 dar; /* DECO Avail Register */ > u32 drr; /* DECO Reset Register */ > u8 res5[0x4d8]; >-- >2.17.1 > >_______________________________________________ >u-boot mailing list >u-boot@linux.nxdi.nxp.com >https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flinux.nx >di.nxp.com%2Fmailman%2Flistinfo%2Fu- >boot&data=02%7C01%7Cpriyanka.jain%40nxp.com%7C156db694a8db47 >894e7708d752e37b7e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C >637069009296949567&sdata=7qWllov0N5cxFDtlJfjLQJu35aM2jYZfKN0nf2 >hYkdQ%3D&reserved=0
On 18.10.2019 09:20, Priyanka Jain wrote: > > >> -----Original Message----- >> From: u-boot-bounces@linux.nxdi.nxp.com <u-boot- >> bounces@linux.nxdi.nxp.com> On Behalf Of Laurentiu Tudor >> Sent: Thursday, October 17, 2019 2:52 PM >> To: u-boot@lists.denx.de; Prabhakar X <prabhakar.kushwaha@nxp.com> >> Subject: [u-boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform >> devices >> >> From: Laurentiu Tudor <laurentiu.tudor@nxp.com> >> >> Add ICID setup for the platform devices contained on this chip: usb, sata, >> sdhc, sec. >> >> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> >> --- >> arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + >> .../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++++++++++++++++++ >> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- >> .../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +- >> .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 + >> board/freescale/lx2160a/lx2160a.c | 2 + >> include/fsl_sec.h | 3 +- >> 7 files changed, 58 insertions(+), 4 deletions(-) create mode 100644 >> arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile >> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile >> index f00ef817b1..e398aecd12 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile >> @@ -24,6 +24,7 @@ endif >> >> ifneq ($(CONFIG_ARCH_LX2160A),) >> obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o >> +obj-y += icid.o lx2160_ids.o >> endif >> >> ifneq ($(CONFIG_ARCH_LS2080A),) >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >> b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >> new file mode 100644 >> index 0000000000..3a0ed1fa55 >> --- /dev/null >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >> @@ -0,0 +1,48 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright 2019 NXP >> + */ >> + >> +#include <common.h> >> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> >> +#include <asm/arch-fsl-layerscape/fsl_icid.h> >> +#include <asm/arch-fsl-layerscape/fsl_portals.h> >> + >> +struct icid_id_table icid_tbl[] = { >> + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), >> + SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID), >> + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), >> + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), >> + SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID), >> + SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID), >> + SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID), >> + SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID), #ifdef >> +CONFIG_FSL_CAAM >> + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), >> + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), >> + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), >> + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), >> + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), >> + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), >> + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), >> + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID), #endif }; >> + >> +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> index 924f5f3fe8..4dea8361fc 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> @@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void) #endif >> >> #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ >> - defined(CONFIG_ARCH_LS2080A) >> + defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) >> set_icids(); >> #endif >> } >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >> index 0e4bf331fd..f86835a33d 100644 >> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >> @@ -447,7 +447,9 @@ struct ccsr_gur { >> u8 res_538[0x550 - 0x538]; /* add more registers when needed */ >> u32 sata1_amqr; >> u32 sata2_amqr; >> - u8 res_558[0x570-0x558]; /* add more registers when needed */ >> + u32 sata3_amqr; >> + u32 sata4_amqr; >> + u8 res_558[0x570 - 0x560]; /* add more registers when needed */ > This will change the byte position for below variables. > Please confirm that you have cross-checked and tested this update for all lsch3 SoC I'm adding 8 bytes but adjusting the res_558 (which btw, I should rename it to res_560) by subtracting the previously added 8 bytes, so things should align properly as before. --- Best Regards, Laurentiu
On 10/17/2019 12:22 PM, Laurentiu Tudor wrote: > From: Laurentiu Tudor <laurentiu.tudor@nxp.com> > > Add ICID setup for the platform devices contained on this chip: usb, > sata, sdhc, sec. > > Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Thanks, Horia
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index f00ef817b1..e398aecd12 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -24,6 +24,7 @@ endif ifneq ($(CONFIG_ARCH_LX2160A),) obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +obj-y += icid.o lx2160_ids.o endif ifneq ($(CONFIG_ARCH_LS2080A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c new file mode 100644 index 0000000000..3a0ed1fa55 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> + +struct icid_id_table icid_tbl[] = { + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID), + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID), + SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID), + SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID), + SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID), +#ifdef CONFIG_FSL_CAAM + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID), +#endif +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 924f5f3fe8..4dea8361fc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void) #endif #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ - defined(CONFIG_ARCH_LS2080A) + defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) set_icids(); #endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 0e4bf331fd..f86835a33d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -447,7 +447,9 @@ struct ccsr_gur { u8 res_538[0x550 - 0x538]; /* add more registers when needed */ u32 sata1_amqr; u32 sata2_amqr; - u8 res_558[0x570-0x558]; /* add more registers when needed */ + u32 sata3_amqr; + u32 sata4_amqr; + u8 res_558[0x570 - 0x560]; /* add more registers when needed */ u32 misc1_amqr; u8 res_574[0x590-0x574]; /* add more registers when needed */ u32 spare1_amqr; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 93bdcc4caa..0b36416ad3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -108,5 +108,7 @@ #define FSL_EDMA_STREAM_ID 70 #define FSL_GPU_STREAM_ID 71 #define FSL_DISPLAY_STREAM_ID 72 +#define FSL_SATA3_STREAM_ID 73 +#define FSL_SATA4_STREAM_ID 74 #endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index b509c0312e..eff12747b4 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -27,6 +27,7 @@ #include "../common/qixis.h" #include "../common/vid.h" #include <fsl_immap.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> #ifdef CONFIG_EMC2305 #include "../common/emc2305.h" @@ -684,6 +685,7 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fsl_mc_fixup_iommu_map_entry(blob); fdt_fixup_board_enet(blob); #endif + fdt_fixup_icid(blob); return 0; } diff --git a/include/fsl_sec.h b/include/fsl_sec.h index be08a2b88b..c0d2c7e866 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -93,8 +93,7 @@ typedef struct ccsr_sec { struct { u32 ms; /* DECO LIODN Register, MS */ u32 ls; /* DECO LIODN Register, LS */ - } decoliodnr[8]; - u8 res4[0x40]; + } decoliodnr[16]; u32 dar; /* DECO Avail Register */ u32 drr; /* DECO Reset Register */ u8 res5[0x4d8];