From patchwork Wed Oct 16 21:04:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 1178180 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-511158-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="hZZwfV+Y"; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="B7BehT/A"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46tlDx2XyDz9sPV for ; Thu, 17 Oct 2019 08:05:21 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=vQNOMWrV+Pba/nrHm8DNqwGX4kmbza47r7IaZhcci65f/dNngP1iE adSnhqHgHk/eXg1ASjcSExtSJtf7NssqhNb/iYxJFbvXtNwBzmhvxolp/rLAvrfG opw7t36cKO8lyEizi7kDmjdqwcdp4cer1qITqItemPzlq1e8usJTEg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=Tg1sdJ2au7xevORE55TF3AaMVKU=; b=hZZwfV+YW9M5yLkeNFIT PRAjlaLVPllVBMePr0h0fazytfiHXk3f0N/GZ5Mhps5YuPyS1LoAQRfMF8JppdCq i5VH+Q9FsU6IcgPsOsdnXucJY89yk+VOQSOM7a9Z14YB3dV4RI2hRdGTVRFQZLG4 KFf0lNRRlzmp4qBZgHFfdhE= Received: (qmail 3222 invoked by alias); 16 Oct 2019 21:05:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 3214 invoked by uid 89); 16 Oct 2019 21:05:14 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-pf1-f195.google.com Received: from mail-pf1-f195.google.com (HELO mail-pf1-f195.google.com) (209.85.210.195) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 16 Oct 2019 21:05:12 +0000 Received: by mail-pf1-f195.google.com with SMTP id x127so155260pfb.7 for ; Wed, 16 Oct 2019 14:05:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nFCjBSJNSVEM2WZH1I/GT9gSjhaiI6O+3DzeNhgh6WA=; b=B7BehT/AdE+lxDmCbOpliAPR/L2EAZ7ghZNF7C9p+du7Lci/iWEk0CwnOIsX6hX1aS FA4B6sFz0mtXKzhxbgCSQTTK3pRQxAeO5vwBoKHYitP8kXXxS3uj2ANMtIkhm7PxA2CX 5pXAWLWvi/9beYYKlNW3FvW+kouc9IuOnxzXz9ri5gznT7zySMNwIE1ttccQkbnhULY7 F3m6ea9MZToSznSb/8jTuFhx/jBJuRqmHsFHOEkj8I88FGha7DSdj/P/UIPUYLEsl0gu BVbIviqq6daXm1bjbJZmtZaH6e+zWUVlFEL8FK2UCJj503hq74cldN0+77is/rUulNiB 2b6w== Received: from rohan.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id m34sm47888222pgb.91.2019.10.16.14.05.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 14:05:10 -0700 (PDT) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: andrew.burgess@embecosm.com, Jim Wilson Subject: [PATCH] RISC-V: Include more registers in SIBCALL_REGS. Date: Wed, 16 Oct 2019 14:04:45 -0700 Message-Id: <20191016210445.20232-1-jimw@sifive.com> In-Reply-To: References: X-IsSubscribed: yes This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19. This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS. It also adds the missing riscv_regno_to_class change. Tested with cross riscv32-elf and riscv64-linux toolchain build and check. There were no regressions. I see about a 0.01% code size reduction for the C and libstdc++ libraries. Committed. Jim gcc/ * config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing regs to SIBCALL_REGS. * config/riscv/riscv.c (riscv_regno_to_class): Change argument passing regs to SIBCALL_REGS. --- gcc/config/riscv/riscv.c | 6 +++--- gcc/config/riscv/riscv.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index b8a8778b92c..77a3ad94aa8 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -256,9 +256,9 @@ enum riscv_microarchitecture_type riscv_microarchitecture; const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, SIBCALL_REGS, SIBCALL_REGS, - JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, - JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, - JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, + JALR_REGS, JALR_REGS, SIBCALL_REGS, SIBCALL_REGS, + SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, + SIBCALL_REGS, SIBCALL_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 5fc9be8edbf..246494663f6 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -400,7 +400,7 @@ enum reg_class #define REG_CLASS_CONTENTS \ { \ { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ - { 0xf00000c0, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \ + { 0xf003fcc0, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \ { 0xffffffc0, 0x00000000, 0x00000000 }, /* JALR_REGS */ \ { 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \