Commit: RX: Codegen bug fixes

Submitted by Nick Clifton on Oct. 5, 2011, 10:23 a.m.

Details

Message ID m3sjn7lot7.fsf@redhat.com
State New
Headers show

Commit Message

Nick Clifton Oct. 5, 2011, 10:23 a.m.
Hi Guys,

  I am applying the patch below to fix a couple of bugs in the RX's
  machine description patterns.  The first concerns the tablejump
  pattern, which needs to include a label to be referenced by the
  ASM_OUTPUT_ADDR_DIFF_ELT macro.

  The second problem is the ADDDI3 spiltter which was not marking its
  first output operand (operand 0) as early clobbered.  This meant that
  it could be used as one of the inputs to the second part of the
  pattern (operands 4,5), causing chaos.

  The final fix was pointed out by Richard Henderson.  The recently
  added support for narrow mode min and max instructions did not work
  for the SMAX insn, as the RX does not have narrow mode versions of
  this insn.

Cheers
  Nick

gcc/ChangeLog
2011-10-05  Nick Clifton  <nickc@redhat.com>

	* config/rx/rx.md (tablejump): Add missing label.
	(adddi3_internal): Mark operand 0 as early-clobbered.
	(smaxsi3): Revert previous delta.
	(adc_internal): Fix whitespace in generated asm.
	(adc_flags): Likewise.

Comments

Richard Henderson Oct. 5, 2011, 11:34 p.m.
On 10/05/2011 03:23 AM, Nick Clifton wrote:
>   The final fix was pointed out by Richard Henderson.  The recently
>   added support for narrow mode min and max instructions did not work
>   for the SMAX insn, as the RX does not have narrow mode versions of
>   this insn.

The SMIN pattern has the same problem.


r~
Nick Clifton Oct. 6, 2011, 10:30 a.m.
Hi Richard,

> The SMIN pattern has the same problem.

*sigh*  Fixed.

Cheers
   Nick

Patch hide | download patch | download mbox

Index: gcc/config/rx/rx.md
===================================================================
--- gcc/config/rx/rx.md	(revision 179540)
+++ gcc/config/rx/rx.md	(working copy)
@@ -332,7 +332,7 @@ 
   ""
   { return flag_pic ? (TARGET_AS100_SYNTAX ? "\n?:\tbra\t%0"
 					   : "\n1:\tbra\t%0")
-	                                   : "jmp\t%0";
+	                                   : "\n1:jmp\t%0";
   }
   [(set_attr "timings" "33")
    (set_attr "length" "2")]
@@ -901,7 +901,7 @@ 
 	  (match_operand:SI   2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
     (clobber (reg:CC CC_REG))]
   "reload_completed"
-  "adc %2,%0"
+  "adc\t%2, %0"
   [(set_attr "timings" "11,11,11,11,11,33")
    (set_attr "length"   "3,4,5,6,7,6")]
 )
@@ -922,7 +922,7 @@ 
 	    (match_dup 2))
 	  (const_int 0)))]
   "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
-  "adc %2,%0"
+  "adc\t%2, %0"
   [(set_attr "timings" "11,11,11,11,11,33")
    (set_attr "length"   "3,4,5,6,7,6")]
 )
@@ -980,7 +980,7 @@ 
 })
 
 (define_insn_and_split "adddi3_internal"
-  [(set (match_operand:SI          0 "register_operand"  "=r")
+  [(set (match_operand:SI          0 "register_operand"  "=&r")
 	(plus:SI (match_operand:SI 2 "register_operand"  "r")
 		 (match_operand:SI 3 "rx_source_operand" "riQ")))
    (set (match_operand:SI          1 "register_operand"  "=r")
@@ -1163,11 +1163,11 @@ 
    (set_attr "timings" "22,44")]
 )
 
-(define_insn "smax<int_modes:mode>3"
-  [(set (match_operand:int_modes                 0 "register_operand" "=r,r,r,r,r,r")
-	(smax:int_modes (match_operand:int_modes 1 "register_operand" "%0,0,0,0,0,0")
-			(match_operand:int_modes 2 "rx_source_operand"
-						 "r,Sint08,Sint16,Sint24,i,Q")))]
+(define_insn "smaxsi3"
+  [(set (match_operand:SI          0 "register_operand" "=r,r,r,r,r,r")
+	(smax:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
+		 (match_operand:SI 2 "rx_source_operand"
+				   "r,Sint08,Sint16,Sint24,i,Q")))]
   ""
   "max\t%Q2, %0"
   [(set_attr "length" "3,4,5,6,7,6")