diff mbox series

V6, #2 of 17: Minor code reformat

Message ID 20191016133854.GB4483@ibm-toto.the-meissners.org
State New
Headers show
Series V6, #2 of 17: Minor code reformat | expand

Commit Message

Michael Meissner Oct. 16, 2019, 1:38 p.m. UTC 
This patch tweaks the code formatting that I noticed in making the previous
patch for some of the 128-bit mode move instructions.  Originally this was part
of V5 patch #2, but it has been moved to a separate patch.

Along with the other patches, I have done bootstraps on a little endian power8
system, and there were no regressions in the test suite.  I have built both
Spec 2006 and Spec 2017 with all of these patches installed using -mcpu=future,
and there were no failures.  Can I check this into the trunk?

Note, I may have limited email access on October 17th and 18th, 2019.

2019-10-15  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.md (mov<mode>_64bit_dm): Reformat.
	(movtd_64bit_nodm): Reformat.
	(mov<mode>_32bit): Reformat.
	(mov<mode>_softfloat): Reformat.
	(FMOVE128_GPR splitter): Reformat.
	(DIFD splitter): Reformat.
	(TI2 splitter): Reformat.

Comments

Segher Boessenkool Oct. 22, 2019, 10:38 p.m. UTC | #1 
Hi!

On Wed, Oct 16, 2019 at 09:38:54AM -0400, Michael Meissner wrote:
> This patch tweaks the code formatting that I noticed in making the previous
> patch for some of the 128-bit mode move instructions.  Originally this was part
> of V5 patch #2, but it has been moved to a separate patch.

> @@ -7792,7 +7795,10 @@ (define_insn_and_split "*movtd_64bit_nod
>    "#"
>    "&& reload_completed"
>    [(pc)]
> -{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
> +{
> +  rs6000_split_multireg_move (operands[0], operands[1]);
> +  DONE;}
> +
>    [(set_attr "length" "8,8,8,12,12,8")
>     (set_attr "max_prefixed_insns" "2")
>     (set_attr "num_insns" "2,2,2,3,3,2")])

Newline before the } here, and no empty line after.  Like all the rest ;-)

Okay with that fixed.  Thanks!


Segher
diff mbox series

Patch

Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 277018)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -7777,7 +7777,10 @@  (define_insn_and_split "*mov<mode>_64bit
   "#"
   "&& reload_completed"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+}
   [(set_attr "length" "8")
    (set_attr "isa" "*,*,*,*,*,*,*,*,p8v,p8v")
    (set_attr "max_prefixed_insns" "2")
@@ -7792,7 +7795,10 @@  (define_insn_and_split "*movtd_64bit_nod
   "#"
   "&& reload_completed"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;}
+
   [(set_attr "length" "8,8,8,12,12,8")
    (set_attr "max_prefixed_insns" "2")
    (set_attr "num_insns" "2,2,2,3,3,2")])
@@ -7809,7 +7815,10 @@  (define_insn_and_split "*mov<mode>_32bit
   "#"
   "&& reload_completed"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+}
   [(set_attr "length" "8,8,8,8,20,20,16")])
 
 (define_insn_and_split "*mov<mode>_softfloat"
@@ -7821,7 +7830,10 @@  (define_insn_and_split "*mov<mode>_softf
   "#"
   "&& reload_completed"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+}
   [(set_attr_alternative "length"
        [(if_then_else (match_test "TARGET_POWERPC64")
 	    (const_string "8")
@@ -8613,7 +8625,10 @@  (define_split
        || (!vsx_register_operand (operands[0], <MODE>mode)
            && !vsx_register_operand (operands[1], <MODE>mode)))"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+})
 
 ;; Move SFmode to a VSX from a GPR register.  Because scalar floating point
 ;; type is stored internally as double precision in the VSX registers, we have
@@ -8803,7 +8818,10 @@  (define_split
    && gpr_or_gpr_p (operands[0], operands[1])
    && !direct_move_p (operands[0], operands[1])"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+})
 
 ;;              GPR store  GPR load   GPR move   GPR li     GPR lis     GPR #
 ;;              FPR store  FPR load   FPR move   AVX store  AVX store   AVX load
@@ -9030,7 +9048,10 @@  (define_split
    && !direct_move_p (operands[0], operands[1])
    && !quad_load_store_p (operands[0], operands[1])"
   [(pc)]
-{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+})
 
 (define_expand "setmemsi"
   [(parallel [(set (match_operand:BLK 0 "")