[12/13] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
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Message ID 20191016113117.12370-13-kishon@ti.com
State Superseded
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Series
  • PHY: Add support for SERDES in TI's J721E SoC
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Commit Message

Kishon Vijay Abraham I Oct. 16, 2019, 11:31 a.m. UTC
Add DT binding documentation for WIZ (SERDES wrapper). WIZ is *NOT* a
PHY but a wrapper used to configure some of the input signals to the
SERDES. It is used with both Sierra(16G) and Torrent(10G) serdes.

Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[jsarha@ti.com: Add separate compatible for Sierra(16G) and Torrent(10G)
 SERDES]
Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 .../bindings/phy/ti,phy-j721e-wiz.txt         | 95 +++++++++++++++++++
 1 file changed, 95 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt

Patch
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diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt
new file mode 100644
index 000000000000..19b4c3e855d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt
@@ -0,0 +1,95 @@ 
+TI J721E WIZ (SERDES Wrapper)
+
+Required properties:
+ - compatible: Should be "ti,j721e-wiz-16g" for Sierra phy wrapper,
+	       or "ti,j721e-wiz-10g" for Torrent phy wrapper.
+ - #address-cells : should be 2 to indicate the child node should use 2 cell
+     for address
+ - #size-cells: should be 2 to indicate the child node should use 2 cell for
+     size
+ - power-domains: As documented by the generic PM domain bindings in
+     Documentation/devicetree/bindings/power/power_domain.txt.
+ - clocks: clock-specifier to represent input to the WIZ required for WIZ
+     module to be functional
+ - num-lanes: Represents thenumber of lanes enabled in the SoC
+     Should be '2' for Sierra wrapper in J721E
+     Should be '4' for Torrent wrapper in J721E
+ - #reset-cells: As documented by the generic reset bindings in
+     Documentation/devicetree/bindings/reset/reset.txt
+     Should be '1'
+ - ranges: Empty ranges property to describe 1:1 translation between parent
+     address space and child address space
+
+Optional properties:
+assigned-clocks and assigned-clock-parents: As documented in the generic
+clock bindings in Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required subnodes:
+ - Clock Subnode: WIZ node should have '3' subnodes for each of the clock
+     selects it supports. The clock subnodes should have the following names
+	1) pll0_refclk
+	2) pll1_refclk
+	3) refclk_dig
+     Each of these subnodes should clocks, clock-output-names, #clock-cells,
+     assigned-clocks and assigned-clock-parents. All these properties are
+     documented in the generic clock bindings in
+     Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - SERDES Subnode: WIZ node should have '1' subnode for the SERDES
+     *) Sierra SERDES should follow the bindings specified in
+        Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
+     *) Torrent SERDES should follow the bindings specified in
+        Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
+
+Example: Example shows binding for SERDES_16G (Sierra SERDES with WIZ wrapper)
+serdes_wiz0: wiz@5000000 {
+	compatible = "ti,j721e-wiz-16g";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+	clocks = <&k3_clks 292 5>;
+	num-lanes = <2>;
+	#reset-cells = <1>;
+	ranges;
+
+	pll0_refclk: pll0_refclk {
+		clocks = <&k3_clks 292 11>, <&cmn_refclk>;
+		clock-output-names = "pll0_refclk";
+		#clock-cells = <0>;
+		assigned-clocks = <&pll0_refclk>;
+		assigned-clock-parents = <&k3_clks 292 11>;
+	};
+
+	pll1_refclk: pll1_refclk {
+		clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
+		clock-output-names = "pll1_refclk";
+		#clock-cells = <0>;
+		assigned-clocks = <&pll1_refclk>;
+		assigned-clock-parents = <&k3_clks 292 0>;
+	};
+
+	refclk_dig: refclk_dig {
+		clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
+			 <&cmn_refclk>, <&cmn_refclk1>;
+		clock-output-names = "refclk_dig";
+		#clock-cells = <0>;
+		assigned-clocks = <&refclk_dig>;
+		assigned-clock-parents = <&k3_clks 292 11>;
+	};
+
+	serdes0: serdes@5000000 {
+		compatible = "cdns,ti,sierra-phy-t0";
+		reg-names = "serdes";
+		reg = <0x00 0x5000000 0x00 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		resets = <&serdes_wiz0 0>;
+		reset-names = "sierra_reset";
+		pcie0_phy0: link@0 {
+			reg = <0>;
+			cdns,num-lanes = <2>;
+			#phy-cells = <0>;
+			cdns,phy-type = <PHY_TYPE_PCIE>;
+			resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+		};
+	};
+};