From patchwork Tue Oct 15 10:38:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Klaus Jensen X-Patchwork-Id: 1176899 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=irrelevant.dk Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46ssSf2nvqz9sP7 for ; Tue, 15 Oct 2019 21:42:26 +1100 (AEDT) Received: from localhost ([::1]:40154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iKKHX-0000wt-Fz for incoming@patchwork.ozlabs.org; Tue, 15 Oct 2019 06:42:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47704) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iKKEZ-0007Om-I1 for qemu-devel@nongnu.org; Tue, 15 Oct 2019 06:39:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iKKEY-0006Fn-BB for qemu-devel@nongnu.org; Tue, 15 Oct 2019 06:39:19 -0400 Received: from charlie.dont.surf ([128.199.63.193]:54796) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iKKEV-0006Bf-Lc; Tue, 15 Oct 2019 06:39:15 -0400 Received: from apples.localdomain (unknown [194.62.217.57]) by charlie.dont.surf (Postfix) with ESMTPSA id D2599BF879; Tue, 15 Oct 2019 10:39:13 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 05/20] nvme: allow completion queues in the cmb Date: Tue, 15 Oct 2019 12:38:45 +0200 Message-Id: <20191015103900.313928-6-its@irrelevant.dk> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015103900.313928-1-its@irrelevant.dk> References: <20191015103900.313928-1-its@irrelevant.dk> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , Javier Gonzalez , qemu-devel@nongnu.org, Max Reitz , Keith Busch , Paul Durrant , Stephen Bates Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Allow completion queues in the controller memory buffer. This also inlines the nvme_addr_{read,write} functions and adds an nvme_addr_is_cmb helper. Signed-off-by: Klaus Jensen --- hw/block/nvme.c | 38 +++++++++++++++++++++++++++++--------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 16f0fba10b08..daa2367b0863 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -52,14 +52,34 @@ static void nvme_process_sq(void *opaque); -static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size) +static inline bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr) { - if (n->cmbsz && addr >= n->ctrl_mem.addr && - addr < (n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size))) { - memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size); - } else { - pci_dma_read(&n->parent_obj, addr, buf, size); + hwaddr low = n->ctrl_mem.addr; + hwaddr hi = n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size); + + return addr >= low && addr < hi; +} + +static inline void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, + int size) +{ + if (n->cmbsz && nvme_addr_is_cmb(n, addr)) { + memcpy(buf, (void *) &n->cmbuf[addr - n->ctrl_mem.addr], size); + return; } + + pci_dma_read(&n->parent_obj, addr, buf, size); +} + +static inline void nvme_addr_write(NvmeCtrl *n, hwaddr addr, void *buf, + int size) +{ + if (n->cmbsz && nvme_addr_is_cmb(n, addr)) { + memcpy((void *) &n->cmbuf[addr - n->ctrl_mem.addr], buf, size); + return; + } + + pci_dma_write(&n->parent_obj, addr, buf, size); } static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) @@ -281,6 +301,7 @@ static void nvme_post_cqes(void *opaque) QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) { NvmeSQueue *sq; + NvmeCqe *cqe = &req->cqe; hwaddr addr; if (nvme_cq_full(cq)) { @@ -294,8 +315,7 @@ static void nvme_post_cqes(void *opaque) req->cqe.sq_head = cpu_to_le16(sq->head); addr = cq->dma_addr + cq->tail * n->cqe_size; nvme_inc_cq_tail(cq); - pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe, - sizeof(req->cqe)); + nvme_addr_write(n, addr, (void *) cqe, sizeof(*cqe)); QTAILQ_INSERT_TAIL(&sq->req_list, req, entry); } if (cq->tail != cq->head) { @@ -1401,7 +1421,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0); + NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 1); NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0); NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1);