[v2,2/6] dt-bindings: Add DT binding for PCIE GEN4 EP of the layerscape
diff mbox series

Message ID 20191015083702.21792-3-xiaowei.bao@nxp.com
State New
Delegated to: Lorenzo Pieralisi
Headers show
Series
  • Add the Mobiveil EP and Layerscape Gen4 EP driver support
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Commit Message

Xiaowei Bao Oct. 15, 2019, 8:36 a.m. UTC
Add the documentation for the Device Tree binding of the layerscape
PCIe GEN4 controller with EP mode.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
v2: 
 - remove the status entry in EP Example.

 .../bindings/pci/layerscape-pcie-gen4.txt          | 27 +++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

Comments

Rob Herring Oct. 17, 2019, 7:03 p.m. UTC | #1
On Tue, Oct 15, 2019 at 04:36:58PM +0800, Xiaowei Bao wrote:
> Add the documentation for the Device Tree binding of the layerscape
> PCIe GEN4 controller with EP mode.
> 
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> ---
> v2: 
>  - remove the status entry in EP Example.
> 
>  .../bindings/pci/layerscape-pcie-gen4.txt          | 27 +++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
> index b40fb5d..06f9309 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
> @@ -3,6 +3,8 @@ NXP Layerscape PCIe Gen4 controller
>  This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
>  the common properties defined in mobiveil-pcie.txt.
>  
> +HOST MODE
> +=========
>  Required properties:
>  - compatible: should contain the platform identifier such as:
>    "fsl,lx2160a-pcie"
> @@ -23,7 +25,20 @@ Required properties:
>  - msi-parent : See the generic MSI binding described in
>    Documentation/devicetree/bindings/interrupt-controller/msi.txt.
>  
> -Example:
> +DEVICE MODE
> +=========
> +Required properties:
> +- compatible: should contain the platform identifier such as:
> +  "fsl,lx2160a-pcie-ep"
> +- reg: base addresses and lengths of the PCIe controller register blocks.
> +  "regs": PCIe controller registers.
> +  "addr_space" EP device CPU address.
> +- apio-wins: number of requested apio outbound windows.
> +
> +Optional Property:
> +- max-functions: Maximum number of functions that can be configured (default 1).
> +
> +RC Example:
>  
>  	pcie@3400000 {
>  		compatible = "fsl,lx2160a-pcie";
> @@ -50,3 +65,13 @@ Example:
>  				<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
>  				<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
>  	};
> +
> +EP Example:
> +
> +	pcie_ep@3400000 {

To repeat my previous comment:

pcie-endpoint@...

> +		compatible = "fsl,lx2160a-pcie-ep";
> +		reg = <0x00 0x03400000 0x0 0x00100000
> +		       0x80 0x00000000 0x8 0x00000000>;
> +		reg-names = "regs", "addr_space";
> +		apio-wins = <8>;
> +	};
> -- 
> 2.9.5
>
Xiaowei Bao Oct. 18, 2019, 3:54 a.m. UTC | #2
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 2019年10月18日 3:03
> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; bhelgaas@google.com;
> mark.rutland@arm.com; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; kishon@ti.com; lorenzo.pieralisi@arm.com; M.h. Lian
> <minghuan.lian@nxp.com>; andrew.murray@arm.com; Mingkai Hu
> <mingkai.hu@nxp.com>; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 2/6] dt-bindings: Add DT binding for PCIE GEN4 EP of
> the layerscape
> 
> On Tue, Oct 15, 2019 at 04:36:58PM +0800, Xiaowei Bao wrote:
> > Add the documentation for the Device Tree binding of the layerscape
> > PCIe GEN4 controller with EP mode.
> >
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > ---
> > v2:
> >  - remove the status entry in EP Example.
> >
> >  .../bindings/pci/layerscape-pcie-gen4.txt          | 27
> +++++++++++++++++++++-
> >  1 file changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
> > index b40fb5d..06f9309 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
> > @@ -3,6 +3,8 @@ NXP Layerscape PCIe Gen4 controller  This PCIe
> > controller is based on the Mobiveil PCIe IP and thus inherits all  the
> > common properties defined in mobiveil-pcie.txt.
> >
> > +HOST MODE
> > +=========
> >  Required properties:
> >  - compatible: should contain the platform identifier such as:
> >    "fsl,lx2160a-pcie"
> > @@ -23,7 +25,20 @@ Required properties:
> >  - msi-parent : See the generic MSI binding described in
> >    Documentation/devicetree/bindings/interrupt-controller/msi.txt.
> >
> > -Example:
> > +DEVICE MODE
> > +=========
> > +Required properties:
> > +- compatible: should contain the platform identifier such as:
> > +  "fsl,lx2160a-pcie-ep"
> > +- reg: base addresses and lengths of the PCIe controller register blocks.
> > +  "regs": PCIe controller registers.
> > +  "addr_space" EP device CPU address.
> > +- apio-wins: number of requested apio outbound windows.
> > +
> > +Optional Property:
> > +- max-functions: Maximum number of functions that can be configured
> (default 1).
> > +
> > +RC Example:
> >
> >  	pcie@3400000 {
> >  		compatible = "fsl,lx2160a-pcie";
> > @@ -50,3 +65,13 @@ Example:
> >  				<0000 0 0 3 &gic 0 0 GIC_SPI 111
> IRQ_TYPE_LEVEL_HIGH>,
> >  				<0000 0 0 4 &gic 0 0 GIC_SPI 112
> IRQ_TYPE_LEVEL_HIGH>;
> >  	};
> > +
> > +EP Example:
> > +
> > +	pcie_ep@3400000 {
> 
> To repeat my previous comment:

Sorry, I missed this comment.

Thanks
Xiaowei

> 
> pcie-endpoint@...
> 
> > +		compatible = "fsl,lx2160a-pcie-ep";
> > +		reg = <0x00 0x03400000 0x0 0x00100000
> > +		       0x80 0x00000000 0x8 0x00000000>;
> > +		reg-names = "regs", "addr_space";
> > +		apio-wins = <8>;
> > +	};
> > --
> > 2.9.5
> >

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
index b40fb5d..06f9309 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
@@ -3,6 +3,8 @@  NXP Layerscape PCIe Gen4 controller
 This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
 the common properties defined in mobiveil-pcie.txt.
 
+HOST MODE
+=========
 Required properties:
 - compatible: should contain the platform identifier such as:
   "fsl,lx2160a-pcie"
@@ -23,7 +25,20 @@  Required properties:
 - msi-parent : See the generic MSI binding described in
   Documentation/devicetree/bindings/interrupt-controller/msi.txt.
 
-Example:
+DEVICE MODE
+=========
+Required properties:
+- compatible: should contain the platform identifier such as:
+  "fsl,lx2160a-pcie-ep"
+- reg: base addresses and lengths of the PCIe controller register blocks.
+  "regs": PCIe controller registers.
+  "addr_space" EP device CPU address.
+- apio-wins: number of requested apio outbound windows.
+
+Optional Property:
+- max-functions: Maximum number of functions that can be configured (default 1).
+
+RC Example:
 
 	pcie@3400000 {
 		compatible = "fsl,lx2160a-pcie";
@@ -50,3 +65,13 @@  Example:
 				<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 				<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 	};
+
+EP Example:
+
+	pcie_ep@3400000 {
+		compatible = "fsl,lx2160a-pcie-ep";
+		reg = <0x00 0x03400000 0x0 0x00100000
+		       0x80 0x00000000 0x8 0x00000000>;
+		reg-names = "regs", "addr_space";
+		apio-wins = <8>;
+	};