[U-Boot,v5,12/19] drivers: Enable cache driver build in SPL

Message ID	1570787542-40896-13-git-send-email-ley.foon.tan@intel.com
State	Superseded
Delegated to:	Simon Goldschmidt
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Ley Foon Tan <ley.foon.tan@intel.com> To: u-boot@lists.denx.de Date: Fri, 11 Oct 2019 17:52:15 +0800 Message-Id: <1570787542-40896-13-git-send-email-ley.foon.tan@intel.com> In-Reply-To: <1570787542-40896-1-git-send-email-ley.foon.tan@intel.com> References: <1570787542-40896-1-git-send-email-ley.foon.tan@intel.com> Cc: Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, Chin Liang See <chin.liang.see@intel.com>, Chee Hong Ang <chee.hong.ang@intel.com> Subject: [U-Boot] [PATCH v5 12/19] drivers: Enable cache driver build in SPL Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	Add Intel Agilex SoC support \| expand [U-Boot,v5,00/19] Add Intel Agilex SoC support [U-Boot,v5,01/19] arm: socfpga: agilex: Add base address for Intel Agilex SoC [U-Boot,v5,02/19] arm: socfpga: Move firewall code to firewall file [U-Boot,v5,03/19] arm: socfpga: Move Stratix10 and Agilex reset manager common code [U-Boot,v5,04/19] arm: socfpga: agilex: Add reset manager support [U-Boot,v5,05/19] arm: socfpga: Move Stratix10 and Agilex system manager common code [U-Boot,v5,06/19] arm: socfpga: agilex: Add system manager support [U-Boot,v5,07/19] arm: socfpga: Move Stratix10 and Agilex clock manager common code [U-Boot,v5,08/19] arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz [U-Boot,v5,09/19] clk: agilex: Add clock driver for Agilex [U-Boot,v5,10/19] arm: socfpga: agilex: Add clock wrapper functions [U-Boot,v5,11/19] cache: Add Arteris Ncore cache coherent unit driver [U-Boot,v5,12/19] drivers: Enable cache driver build in SPL [U-Boot,v5,13/19] arm: agilex: Add clock handoff offset for Agilex [U-Boot,v5,14/19] ddr: altera: Restructure Stratix 10 SDRAM driver [U-Boot,v5,15/19] ddr: altera: agilex: Add SDRAM driver for Agilex [U-Boot,v5,16/19] board: intel: agilex: Add socdk board support for Intel Agilex SoC [U-Boot,v5,17/19] arm: socfpga: agilex: Add SPL for Agilex SoC [U-Boot,v5,18/19] arm: dts: agilex: Add base dtsi and devkit dts [U-Boot,v5,19/19] arm: socfpga: agilex: Enable Agilex SoC build

Message ID

1570787542-40896-13-git-send-email-ley.foon.tan@intel.com

State

Superseded

Delegated to:

Simon Goldschmidt

Headers

From: Ley Foon Tan <ley.foon.tan@intel.com>
To: u-boot@lists.denx.de
Date: Fri, 11 Oct 2019 17:52:15 +0800
Message-Id: <1570787542-40896-13-git-send-email-ley.foon.tan@intel.com>
In-Reply-To: <1570787542-40896-1-git-send-email-ley.foon.tan@intel.com>
References: <1570787542-40896-1-git-send-email-ley.foon.tan@intel.com>
Cc: Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, 
	Chin Liang See <chin.liang.see@intel.com>,
	Chee Hong Ang <chee.hong.ang@intel.com>
Subject: [U-Boot] [PATCH v5 12/19] drivers: Enable cache driver build in SPL
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Series

Add Intel Agilex SoC support | expand

Comments

Simon Goldschmidt Oct. 22, 2019, 6:34 p.m. UTC | #1

Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
> Enable cache driver build in SPL.
> 
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
>   drivers/Makefile | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/Makefile b/drivers/Makefile
> index a4bb5e4975..0d231cddbb 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -30,6 +30,7 @@ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
>   ifndef CONFIG_TPL_BUILD
>   ifdef CONFIG_SPL_BUILD
>   
> +obj-$(CONFIG_CACHE) += cache/

Hmm, I'm not sure this can go in via the socfpga tree (in this series). 
Does this change break any existing configs?

You'd probably have to run this separate from this series so that Tom or 
Simon (Glass) can apply it...?

Regards,
Simon

>   obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/
>   obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
>   obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
>

Ley Foon Tan Oct. 25, 2019, 9:25 a.m. UTC | #2

On Wed, Oct 23, 2019 at 2:34 AM Simon Goldschmidt
<simon.k.r.goldschmidt@gmail.com> wrote:
>
> Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
> > Enable cache driver build in SPL.
> >
> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> > ---
> >   drivers/Makefile | 1 +
> >   1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/Makefile b/drivers/Makefile
> > index a4bb5e4975..0d231cddbb 100644
> > --- a/drivers/Makefile
> > +++ b/drivers/Makefile
> > @@ -30,6 +30,7 @@ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
> >   ifndef CONFIG_TPL_BUILD
> >   ifdef CONFIG_SPL_BUILD
> >
> > +obj-$(CONFIG_CACHE) += cache/
>
> Hmm, I'm not sure this can go in via the socfpga tree (in this series).
> Does this change break any existing configs?
Tired to compile Cyclone 5 and Arria 10 platform which enable
CONFIG_L2X0_CACHE, no compilation.
>
> You'd probably have to run this separate from this series so that Tom or
> Simon (Glass) can apply it...?
Okay, I will send this patch separately from this series.

Thanks.
Regards
Ley Foon
>
> >   obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/
> >   obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
> >   obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
> >
>

diff --git a/drivers/Makefile b/drivers/Makefile
index a4bb5e4975..0d231cddbb 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -30,6 +30,7 @@  obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
 ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_BUILD
 
+obj-$(CONFIG_CACHE) += cache/
 obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/
 obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/

[U-Boot,v5,12/19] drivers: Enable cache driver build in SPL

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