diff mbox

Minor fixups to the sparc bmask/bshuffle patterns.

Message ID 20111003.124344.896972811782018205.davem@davemloft.net
State New
Headers show

Commit Message

David Miller Oct. 3, 2011, 4:43 p.m. UTC 
Committed to trunk.

gcc/

	* config/sparc/sparc.md (bmask<P:mode>_vis): Split into explicit 'di'
	and 'si' patterns which describe the GSR changes explicitly in the
	RTL using zero_extract.
	(bshuffle<V64I:mode>_vis): Put the GSR use inside of the unspec.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@179465 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog             |    7 +++++++
 gcc/config/sparc/sparc.md |   27 +++++++++++++++++++--------
 2 files changed, 26 insertions(+), 8 deletions(-)

Comments

Richard Henderson Oct. 3, 2011, 5:07 p.m. UTC | #1 
On 10/03/2011 09:43 AM, David Miller wrote:
>  (define_insn "bshuffle<V64I:mode>_vis"
>    [(set (match_operand:V64I 0 "register_operand" "=e")
>          (unspec:V64I [(match_operand:V64I 1 "register_operand" "e")
> -	              (match_operand:V64I 2 "register_operand" "e")]
> -                     UNSPEC_BSHUFFLE))
> -   (use (reg:SI GSR_REG))]
> +	              (match_operand:V64I 2 "register_operand" "e")
> +		      (use (reg:SI GSR_REG))]
> +                     UNSPEC_BSHUFFLE))]

I think I was less than clear here.  You don't need the USE either.
The GSR register is simply a normal (third) input to the unspec.


r~
David Miller Oct. 3, 2011, 5:40 p.m. UTC | #2 
From: Richard Henderson <rth@redhat.com>
Date: Mon, 03 Oct 2011 10:07:26 -0700

> On 10/03/2011 09:43 AM, David Miller wrote:
>>  (define_insn "bshuffle<V64I:mode>_vis"
>>    [(set (match_operand:V64I 0 "register_operand" "=e")
>>          (unspec:V64I [(match_operand:V64I 1 "register_operand" "e")
>> -	              (match_operand:V64I 2 "register_operand" "e")]
>> -                     UNSPEC_BSHUFFLE))
>> -   (use (reg:SI GSR_REG))]
>> +	              (match_operand:V64I 2 "register_operand" "e")
>> +		      (use (reg:SI GSR_REG))]
>> +                     UNSPEC_BSHUFFLE))]
> 
> I think I was less than clear here.  You don't need the USE either.
> The GSR register is simply a normal (third) input to the unspec.

I see, I'll fix this up, thanks Richard.
Hans-Peter Nilsson Oct. 4, 2011, 2:17 a.m. UTC | #3 
On Mon, 3 Oct 2011, David Miller wrote:
> 	* config/sparc/sparc.md (bmask<P:mode>_vis): Split into explicit 'di'
> 	and 'si' patterns which describe the GSR changes explicitly in the
> 	RTL using zero_extract.
> 	(bshuffle<V64I:mode>_vis): Put the GSR use inside of the unspec.

(Heh, so I guess USE wasn't really that canonical. ;-)

Beware, ISTM you've now created an exception to your SPARC VIS
programming model that GSR belongs to the programmer (by analogy
with floating-point rounding) as you're letting gcc modify it.

Maybe have a command-line option controlling this and other
possible GSR-setting SIMD patterns from which vectorization
could benefit?

brgds, H-P
diff mbox

Patch

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 028ce8e..9fcee40 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@ 
+2011-10-03  David S. Miller  <davem@davemloft.net>
+
+	* config/sparc/sparc.md (bmask<P:mode>_vis): Split into explicit 'di'
+	and 'si' patterns which describe the GSR changes explicitly in the
+	RTL using zero_extract.
+	(bshuffle<V64I:mode>_vis): Put the GSR use inside of the unspec.
+
 2011-10-03  Artem Shinkarov  <artyom.shinkaroff@gmail.com>
 
 	* optabs.c (expand_vec_shuffle_expr_p): New function. Checks
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 6990746..c48c979 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -8228,11 +8228,22 @@ 
   "array32\t%r1, %r2, %0"
   [(set_attr "type" "array")])
 
-(define_insn "bmask<P:mode>_vis"
-  [(set (match_operand:P 0 "register_operand" "=r")
-        (plus:P (match_operand:P 1 "register_operand" "rJ")
-                (match_operand:P 2 "register_operand" "rJ")))
-   (clobber (reg:SI GSR_REG))]
+(define_insn "bmaskdi_vis"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (plus:DI (match_operand:DI 1 "register_operand" "rJ")
+                 (match_operand:DI 2 "register_operand" "rJ")))
+   (set (zero_extract:DI (reg:DI GSR_REG) (const_int 32) (const_int 32))
+        (plus:DI (match_dup 1) (match_dup 2)))]
+  "TARGET_VIS2"
+  "bmask\t%r1, %r2, %0"
+  [(set_attr "type" "array")])
+
+(define_insn "bmasksi_vis"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (plus:SI (match_operand:SI 1 "register_operand" "rJ")
+                 (match_operand:SI 2 "register_operand" "rJ")))
+   (set (zero_extract:DI (reg:DI GSR_REG) (const_int 32) (const_int 32))
+        (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
   "TARGET_VIS2"
   "bmask\t%r1, %r2, %0"
   [(set_attr "type" "array")])
@@ -8240,9 +8251,9 @@ 
 (define_insn "bshuffle<V64I:mode>_vis"
   [(set (match_operand:V64I 0 "register_operand" "=e")
         (unspec:V64I [(match_operand:V64I 1 "register_operand" "e")
-	              (match_operand:V64I 2 "register_operand" "e")]
-                     UNSPEC_BSHUFFLE))
-   (use (reg:SI GSR_REG))]
+	              (match_operand:V64I 2 "register_operand" "e")
+		      (use (reg:SI GSR_REG))]
+                     UNSPEC_BSHUFFLE))]
   "TARGET_VIS2"
   "bshuffle\t%1, %2, %0"
   [(set_attr "type" "fga")