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V5, #6 of 15: Make vector load/store instruction length correct with prefixed addresses

Message ID 20191009202620.GF2063@ibm-toto.the-meissners.org
State New
Headers show
Series V5, #6 of 15: Make vector load/store instruction length correct with prefixed addresses | expand

Commit Message

Michael Meissner Oct. 9, 2019, 8:26 p.m. UTC 
This patch updates the instruction length for 128-bit move insns for types that
go into a single vector register.  It is a lot simpler than the previous patch,
which was written before I added the prefixed_length and non_prefixed_length
attributes.

Along with the other patches, I have done bootstraps on a little endian power8
system, and there were no regressions in the test suite.  Can I check this into
the trunk?

2019-10-08  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Make sure the
	instruction length is correct for prefixed loads and stores.

Comments

Segher Boessenkool Oct. 11, 2019, 9:53 p.m. UTC | #1 
Hi!

On Wed, Oct 09, 2019 at 04:26:20PM -0400, Michael Meissner wrote:
> --- gcc/config/rs6000/vsx.md	(revision 276713)
> +++ gcc/config/rs6000/vsx.md	(working copy)
> @@ -1149,10 +1149,14 @@ (define_insn "vsx_mov<mode>_64bit"
>                 "vecstore,  vecload,   vecsimple, mffgpr,    mftgpr,    load,
>                  store,     load,      store,     *,         vecsimple, vecsimple,
>                  vecsimple, *,         *,         vecstore,  vecload")
> -   (set_attr "length"
> +   (set_attr "non_prefixed_length"
>                 "*,         *,         *,         8,         *,         8,
>                  8,         8,         8,         8,         *,         *,
>                  *,         20,        8,         *,         *")
> +   (set_attr "prefixed_length"
> +               "*,         *,         *,         8,         *,         20,
> +                20,        20,        20,        8,         *,         *,
> +                *,         20,        8,         *,         *")

Alternative 13 has non_prefixed_length 20, I wonder what insns that
generates?

Other than that, looks good afaics.


Segher
Michael Meissner Oct. 14, 2019, 9:25 p.m. UTC | #2 
On Fri, Oct 11, 2019 at 04:53:23PM -0500, Segher Boessenkool wrote:
> Hi!
> 
> On Wed, Oct 09, 2019 at 04:26:20PM -0400, Michael Meissner wrote:
> > --- gcc/config/rs6000/vsx.md	(revision 276713)
> > +++ gcc/config/rs6000/vsx.md	(working copy)
> > @@ -1149,10 +1149,14 @@ (define_insn "vsx_mov<mode>_64bit"
> >                 "vecstore,  vecload,   vecsimple, mffgpr,    mftgpr,    load,
> >                  store,     load,      store,     *,         vecsimple, vecsimple,
> >                  vecsimple, *,         *,         vecstore,  vecload")
> > -   (set_attr "length"
> > +   (set_attr "non_prefixed_length"
> >                 "*,         *,         *,         8,         *,         8,
> >                  8,         8,         8,         8,         *,         *,
> >                  *,         20,        8,         *,         *")
> > +   (set_attr "prefixed_length"
> > +               "*,         *,         *,         8,         *,         20,
> > +                20,        20,        20,        8,         *,         *,
> > +                *,         20,        8,         *,         *")
> 
> Alternative 13 has non_prefixed_length 20, I wonder what insns that
> generates?

All of the vector constants that match the constants matched by
easy_altivec_constant.

For example:

	vector int foo (void)
	{
	  return (vector int) { 0, 0, 0, 1 };
	}

generates:

        vspltisw 2,0
        vspltisw 0,1
        vsldoi 2,0,2,12
diff mbox series

Patch

Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md	(revision 276713)
+++ gcc/config/rs6000/vsx.md	(working copy)
@@ -1149,10 +1149,14 @@  (define_insn "vsx_mov<mode>_64bit"
                "vecstore,  vecload,   vecsimple, mffgpr,    mftgpr,    load,
                 store,     load,      store,     *,         vecsimple, vecsimple,
                 vecsimple, *,         *,         vecstore,  vecload")
-   (set_attr "length"
+   (set_attr "non_prefixed_length"
                "*,         *,         *,         8,         *,         8,
                 8,         8,         8,         8,         *,         *,
                 *,         20,        8,         *,         *")
+   (set_attr "prefixed_length"
+               "*,         *,         *,         8,         *,         20,
+                20,        20,        20,        8,         *,         *,
+                *,         20,        8,         *,         *")
    (set_attr "isa"
                "<VSisa>,   <VSisa>,   <VSisa>,   *,         *,         *,
                 *,         *,         *,         *,         p9v,       *,