Patchwork Add missing sparc shift zero extensions, and fix shift attributes.

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Submitter David Miller
Date Oct. 3, 2011, 12:50 a.m.
Message ID <20111002.205022.545130502753260605.davem@davemloft.net>
Download mbox | patch
Permalink /patch/117383/
State New
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Comments

David Miller - Oct. 3, 2011, 12:50 a.m.
This is a patch Richard came up with earlier this year when I had him
look into some excessive sign/zero extensions the compiler was making
on sparc 64-bit.

I finally got around to validating this patch and while doing so noticed
that we've had the instruction attributes screwed up on shifts for quite
some time.

A very long time ago, we used to amit "add x, x, y" for a constant
shift left of one.  But that hack got removed a long time, but when
it got removed the conditional attribute setting was left around.

Committed to trunk.

gcc/

	* config/sparc/sparc.md (ashlsi3, *ashldi3_sp64): Remove
	conditional insn type setting, we always emit a shift.
	(*ashlsi3_extend, *lshrsi3_extend0): New patterns.
	(*lshrsi3_extend): Rename to *lshrsi3_extend1.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@179441 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog                  |    8 ++++++++
 gcc/config/sparc/predicates.md |    5 -----
 gcc/config/sparc/sparc.md      |   36 +++++++++++++++++++++++++++++-------
 3 files changed, 37 insertions(+), 12 deletions(-)

Patch

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0f32049..fbc0b20 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@ 
+2011-10-02  Richard Henderson  <rth@redhat.com>
+	    David S. Miller  <davem@davemloft.net>
+
+	* config/sparc/sparc.md (ashlsi3, *ashldi3_sp64): Remove
+	conditional insn type setting, we always emit a shift.
+	(*ashlsi3_extend, *lshrsi3_extend0): New patterns.
+	(*lshrsi3_extend): Rename to *lshrsi3_extend1.
+
 2011-10-02  Gerald Pfeifer  <gerald@pfeifer.com>
 
 	* invoke.texi (SPARC Options): Refer to GNU/Linux.
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index 21399b5..f0be149 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -24,11 +24,6 @@ 
   (and (match_code "const_int,const_double,const_vector")
        (match_test "op == CONST0_RTX (mode)")))
 
-;; Return true if OP is the one constant for MODE.
-(define_predicate "const_one_operand"
-  (and (match_code "const_int,const_double,const_vector")
-       (match_test "op == CONST1_RTX (mode)")))
-
 ;; Return true if the integer representation of OP is
 ;; all-ones.
 (define_predicate "const_all_ones_operand"
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 03158c7..6990746 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -5814,9 +5814,20 @@ 
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
   return "sll\t%1, %2, %0";
 }
-  [(set (attr "type")
-	(if_then_else (match_operand 2 "const_one_operand" "")
-		      (const_string "ialu") (const_string "shift")))])
+  [(set_attr "type" "shift")])
+
+(define_insn "*ashlsi3_extend"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI
+	  (ashift:SI (match_operand:SI 1 "register_operand" "r")
+		     (match_operand:SI 2 "arith_operand" "rI"))))]
+  "TARGET_ARCH64"
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+  return "sll\t%1, %2, %0";
+}
+  [(set_attr "type" "shift")])
 
 (define_expand "ashldi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -5843,9 +5854,7 @@ 
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
   return "sllx\t%1, %2, %0";
 }
-  [(set (attr "type")
-	(if_then_else (match_operand 2 "const_one_operand" "")
-		      (const_string "ialu") (const_string "shift")))])
+  [(set_attr "type" "shift")])
 
 ;; XXX UGH!
 (define_insn "ashldi3_v8plus"
@@ -5980,10 +5989,23 @@ 
   }
   [(set_attr "type" "shift")])
 
+(define_insn "*lshrsi3_extend0"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI
+	  (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+		       (match_operand:SI 2 "arith_operand" "rI"))))]
+  "TARGET_ARCH64"
+  {
+    if (GET_CODE (operands[2]) == CONST_INT)
+      operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+    return "srl\t%1, %2, %0";
+  }
+  [(set_attr "type" "shift")])
+
 ;; This handles the case where
 ;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))),
 ;; but combiner "simplifies" it for us.
-(define_insn "*lshrsi3_extend"
+(define_insn "*lshrsi3_extend1"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(and:DI (subreg:DI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
 			   (match_operand:SI 2 "arith_operand" "r")) 0)