diff mbox series

[U-Boot,RESEND,v1,1/3] ARM: dts: dra7: Add usb peripheral nodes in spl

Message ID 20191009103520.18109-2-jjhiblot@ti.com
State Accepted
Commit 6b23f53b0818130ea6c727357ae3d3109b235e50
Delegated to: Tom Rini
Headers show
Series Add support for DFU boot to DRA7-based EVMs | expand

Commit Message

Jean-Jacques Hiblot Oct. 9, 2019, 10:35 a.m. UTC
From: Faiz Abbas <faiz_abbas@ti.com>

Add usb peripheral and usb phy nodes in spl to enable SPL_DFU bootmode.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
---

 arch/arm/dts/dra7-evm-u-boot.dtsi       | 17 +++++++++++++++++
 arch/arm/dts/dra71-evm-u-boot.dtsi      | 17 +++++++++++++++++
 arch/arm/dts/dra72-evm-revc-u-boot.dtsi | 17 +++++++++++++++++
 arch/arm/dts/dra72-evm-u-boot.dtsi      | 23 +++++++++++++++++++++++
 arch/arm/dts/dra76-evm-u-boot.dtsi      | 17 +++++++++++++++++
 arch/arm/dts/omap5-u-boot.dtsi          |  1 +
 6 files changed, 92 insertions(+)
 create mode 100644 arch/arm/dts/dra72-evm-u-boot.dtsi

Comments

Tom Rini Oct. 26, 2019, 12:06 a.m. UTC | #1
On Wed, Oct 09, 2019 at 12:35:18PM +0200, Jean-Jacques Hiblot wrote:

> From: Faiz Abbas <faiz_abbas@ti.com>
> 
> Add usb peripheral and usb phy nodes in spl to enable SPL_DFU bootmode.
> 
> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/arch/arm/dts/dra7-evm-u-boot.dtsi b/arch/arm/dts/dra7-evm-u-boot.dtsi
index badaebc76f..f06c701dbd 100644
--- a/arch/arm/dts/dra7-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra7-evm-u-boot.dtsi
@@ -32,3 +32,20 @@ 
 &mmc2_iodelay_hs200_rev20_conf {
 	u-boot,dm-spl;
 };
+
+&omap_dwc3_1 {
+	u-boot,dm-spl;
+};
+
+&usb1 {
+	u-boot,dm-spl;
+	dr_mode = "peripheral";
+};
+
+&usb2_phy1 {
+	u-boot,dm-spl;
+};
+
+&usb3_phy1 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/dra71-evm-u-boot.dtsi b/arch/arm/dts/dra71-evm-u-boot.dtsi
index f9da15f1c7..b56d4fc9d8 100644
--- a/arch/arm/dts/dra71-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra71-evm-u-boot.dtsi
@@ -44,3 +44,20 @@ 
 &mmc2_iodelay_hs200_rev20_conf {
 	u-boot,dm-spl;
 };
+
+&omap_dwc3_1 {
+	u-boot,dm-spl;
+};
+
+&usb1 {
+	u-boot,dm-spl;
+	dr_mode = "peripheral";
+};
+
+&usb2_phy1 {
+	u-boot,dm-spl;
+};
+
+&usb3_phy1 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
index f9da15f1c7..b56d4fc9d8 100644
--- a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
+++ b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
@@ -44,3 +44,20 @@ 
 &mmc2_iodelay_hs200_rev20_conf {
 	u-boot,dm-spl;
 };
+
+&omap_dwc3_1 {
+	u-boot,dm-spl;
+};
+
+&usb1 {
+	u-boot,dm-spl;
+	dr_mode = "peripheral";
+};
+
+&usb2_phy1 {
+	u-boot,dm-spl;
+};
+
+&usb3_phy1 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/dra72-evm-u-boot.dtsi b/arch/arm/dts/dra72-evm-u-boot.dtsi
new file mode 100644
index 0000000000..6c868f75d1
--- /dev/null
+++ b/arch/arm/dts/dra72-evm-u-boot.dtsi
@@ -0,0 +1,23 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "omap5-u-boot.dtsi"
+
+&omap_dwc3_1 {
+	u-boot,dm-spl;
+};
+
+&usb1 {
+	u-boot,dm-spl;
+	dr_mode = "peripheral";
+};
+
+&usb2_phy1 {
+	u-boot,dm-spl;
+};
+
+&usb3_phy1 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/dra76-evm-u-boot.dtsi b/arch/arm/dts/dra76-evm-u-boot.dtsi
index f651f404e0..a4dfbe7e60 100644
--- a/arch/arm/dts/dra76-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra76-evm-u-boot.dtsi
@@ -24,3 +24,20 @@ 
 &mmc2_iodelay_hs200_conf {
 	u-boot,dm-spl;
 };
+
+&omap_dwc3_1 {
+	u-boot,dm-spl;
+};
+
+&usb1 {
+	u-boot,dm-spl;
+	dr_mode = "peripheral";
+};
+
+&usb2_phy1 {
+	u-boot,dm-spl;
+};
+
+&usb3_phy1 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi
index 1b1d765fae..39071e223d 100644
--- a/arch/arm/dts/omap5-u-boot.dtsi
+++ b/arch/arm/dts/omap5-u-boot.dtsi
@@ -22,6 +22,7 @@ 
 
 		ocp2scp@4a080000 {
 			compatible = "ti,omap-ocp2scp", "simple-bus";
+			u-boot,dm-spl;
 		};
 
 		ocp2scp@4a090000 {