Message ID | 1570612670-29333-2-git-send-email-eugen.hristev@microchip.com |
---|---|
State | Accepted |
Commit | 2d604ed85238d318137dc2a1ee318e9a426524c2 |
Delegated to: | Eugen Hristev |
Headers | show
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Wed, 9 Oct 2019 09:23:40 +0000 From: <Eugen.Hristev@microchip.com> To: <u-boot@lists.denx.de> Thread-Topic: [PATCH 2/6] ARM: dts: sam9x60: add flx0 node Thread-Index: AQHVfoM8Dnnl/2FAdkCQkSs7DEh4aw== Date: Wed, 9 Oct 2019 09:23:40 +0000 Message-ID: <1570612670-29333-2-git-send-email-eugen.hristev@microchip.com> References: <1570612670-29333-1-git-send-email-eugen.hristev@microchip.com> In-Reply-To: <1570612670-29333-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR08CA0144.eurprd08.prod.outlook.com (2603:10a6:800:d5::22) To DM5PR11MB1242.namprd11.prod.outlook.com (2603:10b6:3:14::8) x-mailer: git-send-email 2.7.4 x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3bbd2fe2-33f1-477d-04fe-08d74c9a5f3a x-ms-traffictypediagnostic: DM5PR11MB0025: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: <DM5PR11MB002562B261B6E6A9139ED9BCE8950@DM5PR11MB0025.namprd11.prod.outlook.com> x-ms-oob-tlc-oobclassifiers: OLM:1079; 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[U-Boot,1/6] misc: microchip_flexcom: introduce microchip_flexcom driver
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diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index e01539e..41ac1f1 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -73,6 +73,16 @@ status = "disabled"; }; + flx0: flexcom@f801c600 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf801c000 0x200>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf801c000 0x800>; + status = "disabled"; + }; + macb0: ethernet@f802c000 { compatible = "cdns,sam9x60-macb", "cdns,macb"; reg = <0xf802c000 0x100>; @@ -221,6 +231,11 @@ reg = <3>; }; + flx0_clk: flx0_clk { + #clock-cells = <0>; + reg = <5>; + }; + pioD_clk: pioD_clk { #clock-cells = <0>; reg = <44>;