Patchwork [RFC,2/2] target-arm: Add support for Cortex-R4F

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Submitter Andreas Färber
Date Oct. 2, 2011, 6:56 p.m.
Message ID <1317581808-9784-3-git-send-email-andreas.faerber@web.de>
Download mbox | patch
Permalink /patch/117360/
State New
Headers show

Comments

Andreas Färber - Oct. 2, 2011, 6:56 p.m.
All CPU-dependent initializations are currently done based on MIDR.
Cortex-R4F shares the MIDR with Cortex-R4 though. Therefore consider the
CPU model string, too (which is not cleared on reset).

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <andreas.faerber@web.de>
---
 target-arm/helper.c |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)

Patch

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 21be805..2273492 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -196,6 +196,40 @@  static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         /* TODO other features */
         set_feature(env, ARM_FEATURE_THUMB2);
         set_feature(env, ARM_FEATURE_V7);
+        if (strcmp(env->cpu_model_str, "cortex-r4f") == 0) {
+            uint8_t r = (id >> 20) & 0xf;
+            uint8_t p = id & 0xf;
+            uint8_t rev = 0;
+            set_feature(env, ARM_FEATURE_VFP);
+            set_feature(env, ARM_FEATURE_VFP3);
+            /* TODO VFPv3-D16 */
+            /* Calculate FPSID value matching to MIDR */
+            if (r == 1) {
+                switch (p) {
+                case 0:
+                    rev = 0x3;
+                    break;
+                case 1:
+                    rev = 0x4;
+                    break;
+                case 2:
+                    rev = 0x6;
+                    break;
+                case 3:
+                    rev = 0x7;
+                    break;
+                case 4:
+                    rev = 0x8;
+                    break;
+                }
+            }
+            if (rev == 0) {
+                cpu_abort(env,
+                          "Cortex-R4F r%" PRIu8 "p%" PRIu8 " unsupported",
+                          r, p);
+            }
+            env->vfp.xregs[ARM_VFP_FPSID] = 0x41023140 | (rev & 0xf);
+        }
         memcpy(env->cp15.c0_c1, cortexr4_cp15_c0_c1, 8 * sizeof(uint32_t));
         memcpy(env->cp15.c0_c2, cortexr4_cp15_c0_c2, 8 * sizeof(uint32_t));
         break;
@@ -438,6 +472,7 @@  static const struct arm_cpu_t arm_cpu_names[] = {
     { ARM_CPUID_CORTEXA8, "cortex-a8"},
     { ARM_CPUID_CORTEXA9, "cortex-a9"},
     { ARM_CPUID_CORTEXR4_R1P4, "cortex-r4"},
+    { ARM_CPUID_CORTEXR4_R1P4, "cortex-r4f"},
     { ARM_CPUID_TI925T, "ti925t" },
     { ARM_CPUID_PXA250, "pxa250" },
     { ARM_CPUID_SA1100,    "sa1100" },