From patchwork Tue Oct 8 10:36:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jozef Lawrynowicz X-Patchwork-Id: 1173166 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-510453-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mittosystems.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="PiAesTNe"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=mittosystems.com header.i=@mittosystems.com header.b="gG37U/78"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46nYgs382Yz9sN1 for ; Tue, 8 Oct 2019 21:37:13 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:in-reply-to:references:mime-version :content-type; q=dns; s=default; b=tD7qe4Ug1esHI99FtrdEzs1b63RRI VQ/EM4bIJVIwB7GMYx/M+qj4GC4PCgyf4ICzcNbO37KfgCqFT3CKSkH8rVLLCLU/ IUtGZguizuPbKRWPutg1ftTA/3ZXAUOz9WJuAudhAOq27Y0sDrCgxyHsK7kdZCoS 0JBkHDy3KG8y0A= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:in-reply-to:references:mime-version :content-type; s=default; bh=2r3UzmA5B+9pTBi5/qkBjKHkmbo=; b=PiA esTNe7BCEPz80jJzk83bA+AWbSt/5QrYQCSGVjfIIKNtaLr4cHu/Psij+DUMfKUu gQfu1wLnt+PhDh4OfpZMlKbnf4+qbqvaXARkzxosBOb55qjZQ2KaE+u5OpxtQrxM 6Wc09hoq/oXP2x4iEXo7iAAPxdhqCSaEXXCnfEtc= Received: (qmail 86668 invoked by alias); 8 Oct 2019 10:37:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 86654 invoked by uid 89); 8 Oct 2019 10:37:05 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-21.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-wm1-f48.google.com Received: from mail-wm1-f48.google.com (HELO mail-wm1-f48.google.com) (209.85.128.48) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 08 Oct 2019 10:37:03 +0000 Received: by mail-wm1-f48.google.com with SMTP id r17so2062697wme.0 for ; Tue, 08 Oct 2019 03:37:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mittosystems.com; s=google; h=date:from:to:subject:message-id:in-reply-to:references:mime-version; bh=5FZofE4YvH1l5yheNwFncN2G+cd9oq+3AI/0RKY8umQ=; b=gG37U/78Ym1Lur6qY8DZnOUg6W13sXz+xLdlLrr6H5B16Ml0XjdC7lrr9xmV1GQjr0 I7of9LY7IojPAE/3xBiKeTu2jGKksJbnlZ7EqEON0WcejsruzuQb5rSTUtwWVu+xzkpK ZDLEgV6L3obDeZIbLUWECimX8AFV9ggSrgHyJYHGHD7jgq/fgtHfwN0gcADQuJVWgmni Agk5fRJUUvF3olw+g3DyJNil2Kt/uSbrwa4/pE7rFBH7wMENQdxdTEoctMbVLk5g5MX5 Z55CoS0tUF/ogkzys2NFy07/gAZFBVdhsiL/pS2mXSOLvXJadG4dXo7zia5t4JoAeTmY gjiw== Received: from jozef-kubuntu ([2a01:4b00:87fd:900:dcf5:b2e3:466f:8152]) by smtp.gmail.com with ESMTPSA id 90sm25412586wrr.1.2019.10.08.03.37.01 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Oct 2019 03:37:01 -0700 (PDT) Date: Tue, 8 Oct 2019 11:36:59 +0100 From: Jozef Lawrynowicz To: "gcc-patches@gcc.gnu.org" Subject: [PATCH 1/2][MSP430] Reorder and group zero_extend insns in msp430.md Message-ID: <20191008113659.74466106@jozef-kubuntu> In-Reply-To: <20191008113450.5b6fa184@jozef-kubuntu> References: <20191008113450.5b6fa184@jozef-kubuntu> MIME-Version: 1.0 X-IsSubscribed: yes This is an "obvious" mechanical patch which just reorders and groups the zero_extend insns in msp430.md, in preparation for the next functional patch. From 8810aa7a19569d7e49e898613736d793c43c20a1 Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Mon, 7 Oct 2019 11:24:31 +0100 Subject: [PATCH 1/2] MSP430: Reorder and group zero_extend insns in msp430.md gcc/ChangeLog: 2019-10-08 Jozef Lawrynowicz * config/msp430/msp430.md: Group zero_extend* insns together. --- gcc/config/msp430/msp430.md | 117 ++++++++++++++++++------------------ 1 file changed, 59 insertions(+), 58 deletions(-) diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md index a533efa1656..2e8e8326232 100644 --- a/gcc/config/msp430/msp430.md +++ b/gcc/config/msp430/msp430.md @@ -564,15 +564,11 @@ AND%X0\t#0xff, %0" ) -;; Eliminate extraneous zero-extends mysteriously created by gcc. -(define_peephole2 - [(set (match_operand:HI 0 "register_operand") - (zero_extend:HI (match_operand:QI 1 "general_operand"))) - (set (match_operand:HI 2 "register_operand") - (zero_extend:HI (match_operand:QI 3 "register_operand")))] - "REGNO (operands[0]) == REGNO (operands[2]) && REGNO (operands[2]) == REGNO (operands[3])" - [(set (match_dup 0) - (zero_extend:HI (match_dup 1)))] +(define_insn "zero_extendqisi2" + [(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=r") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] + "" + "MOV%X1.B\t%1,%L0 { CLR\t%H0" ) (define_insn "zero_extendhipsi2" @@ -584,39 +580,6 @@ MOVX.A\t%1, %0" ) -(define_insn "truncpsihi2" - [(set (match_operand:HI 0 "msp430_general_dst_operand" "=rm") - (truncate:HI (match_operand:PSI 1 "register_operand" "r")))] - "" - "MOVX\t%1, %0" -) - -(define_insn "extendhisi2" - [(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=r") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r")))] - "" - { return msp430x_extendhisi (operands); } -) - -(define_insn "extendhipsi2" - [(set (match_operand:PSI 0 "msp430_general_dst_nonv_operand" "=r") - (subreg:PSI (sign_extend:SI (match_operand:HI 1 "general_operand" "0")) 0))] - "msp430x" - "RLAM.A #4, %0 { RRAM.A #4, %0" -) - -;; Look for cases where integer/pointer conversions are suboptimal due -;; to missing patterns, despite us not having opcodes for these -;; patterns. Doing these manually allows for alternate optimization -;; paths. - -(define_insn "zero_extendqisi2" - [(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=r") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] - "" - "MOV%X1.B\t%1,%L0 { CLR\t%H0" -) - (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=rm,r") (zero_extend:SI (match_operand:HI 1 "general_operand" "0,r")))] @@ -635,22 +598,6 @@ MOV.W\t%1,%0" ) -(define_insn "extend_and_shift1_hipsi2" - [(set (subreg:SI (match_operand:PSI 0 "msp430_general_dst_nonv_operand" "=r") 0) - (ashift:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "0")) - (const_int 1)))] - "msp430x" - "RLAM.A #4, %0 { RRAM.A #3, %0" -) - -(define_insn "extend_and_shift2_hipsi2" - [(set (subreg:SI (match_operand:PSI 0 "msp430_general_dst_nonv_operand" "=r") 0) - (ashift:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "0")) - (const_int 2)))] - "msp430x" - "RLAM.A #4, %0 { RRAM.A #2, %0" -) - ; Nasty - we are sign-extending a 20-bit PSI value in one register into ; two adjacent 16-bit registers to make an SI value. There is no MSP430X ; instruction that will do this, so we push the 20-bit value onto the stack @@ -685,6 +632,60 @@ " ) + +;; Eliminate extraneous zero-extends mysteriously created by gcc. +(define_peephole2 + [(set (match_operand:HI 0 "register_operand") + (zero_extend:HI (match_operand:QI 1 "general_operand"))) + (set (match_operand:HI 2 "register_operand") + (zero_extend:HI (match_operand:QI 3 "register_operand")))] + "REGNO (operands[0]) == REGNO (operands[2]) && REGNO (operands[2]) == REGNO (operands[3])" + [(set (match_dup 0) + (zero_extend:HI (match_dup 1)))] +) + +(define_insn "truncpsihi2" + [(set (match_operand:HI 0 "msp430_general_dst_operand" "=rm") + (truncate:HI (match_operand:PSI 1 "register_operand" "r")))] + "" + "MOVX\t%1, %0" +) + +(define_insn "extendhisi2" + [(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=r") + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r")))] + "" + { return msp430x_extendhisi (operands); } +) + +(define_insn "extendhipsi2" + [(set (match_operand:PSI 0 "msp430_general_dst_nonv_operand" "=r") + (subreg:PSI (sign_extend:SI (match_operand:HI 1 "general_operand" "0")) 0))] + "msp430x" + "RLAM.A #4, %0 { RRAM.A #4, %0" +) + +;; Look for cases where integer/pointer conversions are suboptimal due +;; to missing patterns, despite us not having opcodes for these +;; patterns. Doing these manually allows for alternate optimization +;; paths. + +(define_insn "extend_and_shift1_hipsi2" + [(set (subreg:SI (match_operand:PSI 0 "msp430_general_dst_nonv_operand" "=r") 0) + (ashift:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "0")) + (const_int 1)))] + "msp430x" + "RLAM.A #4, %0 { RRAM.A #3, %0" +) + +(define_insn "extend_and_shift2_hipsi2" + [(set (subreg:SI (match_operand:PSI 0 "msp430_general_dst_nonv_operand" "=r") 0) + (ashift:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "0")) + (const_int 2)))] + "msp430x" + "RLAM.A #4, %0 { RRAM.A #2, %0" +) + ;; We also need to be able to sign-extend pointer types (eg ptrdiff_t). ;; Since (we assume) pushing a 20-bit value onto the stack zero-extends ;; it, we use a different method here. -- 2.17.1