| Message ID | 20191005154748.21718-5-f4bug@amsat.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/arm/exynos4210: Add acceptance tests to the SMDKC210 board | expand |
On Sat, Oct 05, 2019 at 05:47:47PM +0200, Philippe Mathieu-Daudé wrote: > The Exynos SoC has specific SDHCI registers. Use the s3c SDHCI > model which handle these specific registers. > > This silents the following "SDHC ... not implemented" warnings so > we can focus on the important registers missing: > > $ qemu-system-arm ... -d unimp \ > -append "... root=/dev/mmcblk0 rootfstype=ext4 rw rootwait" \ > -drive file=linux-build-test/rootfs/arm/rootfs-armv5.ext2,if=sd,format=raw > [...] > [ 25.744858] sdhci: Secure Digital Host Controller Interface driver > [ 25.745862] sdhci: Copyright(c) Pierre Ossman > [ 25.783188] s3c-sdhci 12530000.sdhci: clock source 2: mmc_busclk.2 (12000000 Hz) > SDHC rd_4b @0x80 not implemented > SDHC wr_4b @0x80 <- 0x00000020 not implemented > SDHC wr_4b @0x8c <- 0x00030000 not implemented > SDHC rd_4b @0x80 not implemented > SDHC wr_4b @0x80 <- 0xc0004100 not implemented > SDHC wr_4b @0x84 <- 0x80808080 not implemented > [ 26.013318] mmc0: SDHCI controller on samsung-hsmmc [12530000.sdhci] using ADMA > [ 26.032318] Synopsys Designware Multimedia Card Interface Driver > [ 42.024885] Waiting for root device /dev/mmcblk0... > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > hw/arm/exynos4210.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Best regards, Krzysztof
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index a9f8a5c868..77fbe1baab 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -405,7 +405,7 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) * public datasheet which is very similar (implementing * MMC Specification Version 4.0 being the only difference noted) */ - dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); + dev = qdev_create(NULL, TYPE_S3C_SDHCI); qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); qdev_init_nofail(dev);
The Exynos SoC has specific SDHCI registers. Use the s3c SDHCI model which handle these specific registers. This silents the following "SDHC ... not implemented" warnings so we can focus on the important registers missing: $ qemu-system-arm ... -d unimp \ -append "... root=/dev/mmcblk0 rootfstype=ext4 rw rootwait" \ -drive file=linux-build-test/rootfs/arm/rootfs-armv5.ext2,if=sd,format=raw [...] [ 25.744858] sdhci: Secure Digital Host Controller Interface driver [ 25.745862] sdhci: Copyright(c) Pierre Ossman [ 25.783188] s3c-sdhci 12530000.sdhci: clock source 2: mmc_busclk.2 (12000000 Hz) SDHC rd_4b @0x80 not implemented SDHC wr_4b @0x80 <- 0x00000020 not implemented SDHC wr_4b @0x8c <- 0x00030000 not implemented SDHC rd_4b @0x80 not implemented SDHC wr_4b @0x80 <- 0xc0004100 not implemented SDHC wr_4b @0x84 <- 0x80808080 not implemented [ 26.013318] mmc0: SDHCI controller on samsung-hsmmc [12530000.sdhci] using ADMA [ 26.032318] Synopsys Designware Multimedia Card Interface Driver [ 42.024885] Waiting for root device /dev/mmcblk0... Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- hw/arm/exynos4210.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)