From patchwork Fri Oct 4 16:29:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 1171943 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="D2iEU3IP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46lFhB2hcGz9sNw for ; Sat, 5 Oct 2019 02:29:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730626AbfJDQ31 (ORCPT ); Fri, 4 Oct 2019 12:29:27 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19909 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388549AbfJDQ31 (ORCPT ); Fri, 4 Oct 2019 12:29:27 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 04 Oct 2019 09:29:29 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 04 Oct 2019 09:29:26 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 04 Oct 2019 09:29:26 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 4 Oct 2019 16:29:25 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 4 Oct 2019 16:29:26 +0000 Received: from jckuo-lt.nvidia.com (Not Verified[10.19.101.223]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 04 Oct 2019 09:29:25 -0700 From: JC Kuo To: , , CC: , , , , , , JC Kuo Subject: [PATCH v3 5/7] dt-bindings: phy: tegra: Add Tegra194 support Date: Sat, 5 Oct 2019 00:29:04 +0800 Message-ID: <20191004162906.4818-6-jckuo@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191004162906.4818-1-jckuo@nvidia.com> References: <20191004162906.4818-1-jckuo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1570206569; bh=oPh6i0uVrEseUNCYDKyoJDsvrjCt5XLvlP/lkvSAFLc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=D2iEU3IP2OrF/HW/aFQkFf7pOIGwTolfHIwJSABk4d7aQ6GH6+AdfBVh2/v63MEeb wdKiMy5PNexnjuTJmcwfUx7lMhexYWMC9TN7BITUhBgmuwgKehaDlXABIpzW4sOb5L F69lLEibKQVMtSiCFuEl0e42fGzj/RPEtTuEjjZByq27VCQWxAoWk5wlr3vLVfTuN1 YtRM8K2rk5AFoSLdtvwh6psvrP3CEntgDv8UTdGHkpVInO+DE0E7PcQmbe9mKuuqyM k4R1JWv0XeKrqlHGOwrsnaOdE5oPQDUz7b3FbXdbmOQSSEYaXMN0eZ1oY5QIsx2tf0 +TanqBJ/7sJ0w== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Extend the bindings to cover the set of features found in Tegra194. Note that, technically, there are four more supplies connected to the XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL) , but the power sequencing requirements of Tegra194 require these to be under the control of the PMIC. Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. To deal with this, a new device node property "nvidia,disable-gen2" was added to Tegra194 that be used to specifically disable Gen 2 speed for a particular USB 3.0 port so that the port can be limited to Gen 1 speed and avoid the instability. Signed-off-by: JC Kuo --- Changes in v3: none Changes in v2: - fix a typo .../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt index 9fb682e47c29..59d870fa42e9 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt @@ -37,6 +37,7 @@ Required properties: - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" - Tegra210: "nvidia,tegra210-xusb-padctl" - Tegra186: "nvidia,tegra186-xusb-padctl" + - Tegra194: "nvidia,tegra194-xusb-padctl" - reg: Physical base address and length of the controller's registers. - resets: Must contain an entry for each entry in reset-names. - reset-names: Must include the following entries: @@ -62,6 +63,10 @@ For Tegra186: - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V. +For Tegra194: +- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply + 3.3 V. +- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. Pad nodes: ========== @@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below: - sata: sata-0 - functions: "usb3-ss", "sata" +For Tegra194, the list of valid PHY nodes is given below: +- usb2: usb2-0, usb2-1, usb2-2, usb2-3 + - functions: "xusb" +- usb3: usb3-0, usb3-1, usb3-2, usb3-3 + - functions: "xusb" Port nodes: =========== @@ -221,6 +231,9 @@ Optional properties: is internal. In the absence of this property the port is considered to be external. +- nvidia,disable-gen2: A boolean property whose presence determines that a port + should be limited to USB 3.1 Gen 1. This property is only for Tegra194. + For Tegra124 and Tegra132, the XUSB pad controller exposes the following ports: - 3x USB2: usb2-0, usb2-1, usb2-2 @@ -233,6 +246,9 @@ For Tegra210, the XUSB pad controller exposes the following ports: - 2x HSIC: hsic-0, hsic-1 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 +For Tegra194, the XUSB pad controller exposes the following ports: +- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 +- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 Examples: =========