From patchwork Fri Oct 4 08:19:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 1171607 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="BVu9+Cw1"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46l2qY6SHbz9sPw for ; Fri, 4 Oct 2019 18:20:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388573AbfJDIUD (ORCPT ); Fri, 4 Oct 2019 04:20:03 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:15742 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388549AbfJDIUC (ORCPT ); Fri, 4 Oct 2019 04:20:02 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 04 Oct 2019 01:20:03 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 04 Oct 2019 01:20:00 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 04 Oct 2019 01:20:00 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 4 Oct 2019 08:19:59 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 4 Oct 2019 08:19:59 +0000 Received: from jckuo-lt.nvidia.com (Not Verified[10.19.108.105]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 04 Oct 2019 01:19:59 -0700 From: JC Kuo To: , , CC: , , , , , , JC Kuo Subject: [PATCH v2 6/7] arm64: tegra: Add XUSB and pad controller on Tegra194 Date: Fri, 4 Oct 2019 16:19:40 +0800 Message-ID: <20191004081941.4831-7-jckuo@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191004081941.4831-1-jckuo@nvidia.com> References: <20191004081941.4831-1-jckuo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1570177203; bh=NilRzR9NxfZ2I4uh23VlLGyILJ5OdWsq+Bi1I9dQtFs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=BVu9+Cw1FtZVHyeIhT5iyUN9p5YMOls119+ZTD0rYPNif+LtoQtz5fNMz5EbKf9Ks XU/jnEqQN8kiLKZriG+QmOBvsF4L3orHhXJ1kD8vdxsrjnPdPBULBG/J1qy7xlHUJt AXrwRjPH5g4tZJlSAML8NJk5bU52y59WwBBHFi50Bil9F4kWr0hhDByciweElvWlas 3WrYqFX48WK5NTIQMxU696rFV+aBaVxQHT5MNUIGoTYulWB0uXWuEMczXbMy7kN9qu IBFMlXixo3aBcytSyMIRKPGCvKVdIOMzkOiFJZaJ3XZN5yPUlU9uaxXbi0/MYww+jR ucvYyKEHAZ+Mw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Adds the XUSB pad and XUSB controllers on Tegra194. Signed-off-by: JC Kuo --- Changes in v2: - renamed xhci@3610000 with usb@3610000 - moved padctl@3520000 and usb@3610000 inside /cbb - cleaned up "clocks" property of usb@3610000 node - added blanks lines to visually separate blocks arch/arm64/boot/dts/nvidia/tegra194.dtsi | 139 +++++++++++++++++++++++ 1 file changed, 139 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 3c0cf54f0aab..3c7ea264bc1c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -487,6 +487,145 @@ status = "disabled"; }; + xusb_padctl: padctl@3520000 { + compatible = "nvidia,tegra194-xusb-padctl"; + reg = <0x03520000 0x1000>, + <0x03540000 0x1000>; + reg-names = "padctl", "ao"; + + resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + status = "disabled"; + + pads { + usb2 { + clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + status = "disabled"; + }; + + usb2-2 { + status = "disabled"; + }; + + usb2-3 { + status = "disabled"; + }; + + usb3-0 { + status = "disabled"; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + status = "disabled"; + }; + }; + }; + + usb@3610000 { + compatible = "nvidia,tegra194-xusb"; + reg = <0x03610000 0x40000>, + < 0x03600000 0x10000>; + reg-names = "hcd", "fpci"; + + interrupts = , + , + ; + + clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA194_CLK_XUSB_FALCON>, + <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA194_CLK_XUSB_SS>, + <&bpmp TEGRA194_CLK_CLK_M>, + <&bpmp TEGRA194_CLK_XUSB_FS>, + <&bpmp TEGRA194_CLK_UTMIPLL>, + <&bpmp TEGRA194_CLK_CLK_M>, + <&bpmp TEGRA194_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; + gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;