From patchwork Fri Sep 30 03:52:49 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Liu Yu-B13201 X-Patchwork-Id: 117035 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1EF351007D6 for ; Fri, 30 Sep 2011 15:31:06 +1000 (EST) Received: from localhost ([::1]:55632 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R9VgY-0004gR-CG for incoming@patchwork.ozlabs.org; Fri, 30 Sep 2011 01:30:58 -0400 Received: from eggs.gnu.org ([140.186.70.92]:41643) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R9VgI-00047d-KN for qemu-devel@nongnu.org; Fri, 30 Sep 2011 01:30:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R9VgH-0004kv-Ao for qemu-devel@nongnu.org; Fri, 30 Sep 2011 01:30:42 -0400 Received: from am1ehsobe003.messaging.microsoft.com ([213.199.154.206]:7921 helo=AM1EHSOBE003.bigfish.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R9VgD-0004jx-ET; Fri, 30 Sep 2011 01:30:37 -0400 Received: from mail36-am1-R.bigfish.com (10.3.201.253) by AM1EHSOBE003.bigfish.com (10.3.204.23) with Microsoft SMTP Server id 14.1.225.22; Fri, 30 Sep 2011 05:00:30 +0000 Received: from mail36-am1 (localhost.localdomain [127.0.0.1]) by mail36-am1-R.bigfish.com (Postfix) with ESMTP id B1360DC05A2; Fri, 30 Sep 2011 05:00:30 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-SS: 0, Received: from mail36-am1 (localhost.localdomain [127.0.0.1]) by mail36-am1 (MessageSwitch) id 1317358825583611_20030; Fri, 30 Sep 2011 05:00:25 +0000 (UTC) Received: from AM1EHSMHS004.bigfish.com (unknown [10.3.201.245]) by mail36-am1.bigfish.com (Postfix) with ESMTP id 8A0F9130053; Fri, 30 Sep 2011 05:00:25 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS004.bigfish.com (10.3.207.104) with Microsoft SMTP Server (TLS) id 14.1.225.22; Fri, 30 Sep 2011 05:00:25 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.323.7; Fri, 30 Sep 2011 00:00:21 -0500 Received: from localhost (rock.ap.freescale.net [10.193.20.106]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p8U50Jmc004724; Fri, 30 Sep 2011 00:00:20 -0500 (CDT) From: Liu Yu To: Date: Fri, 30 Sep 2011 11:52:49 +0800 Message-ID: <1317354770-21531-1-git-send-email-yu.liu@freescale.com> X-Mailer: git-send-email 1.6.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-detected-operating-system: by eggs.gnu.org: Windows 2000 SP2+, XP SP1+ (seldom 98) X-Received-From: 213.199.154.206 Cc: Liu Yu , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 1/2] ppc/e500_pci: Fix code style X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Put trailing statements on next line. Signed-off-by: Liu Yu Reviewed-by: Andreas Färber --- hw/ppce500_pci.c | 76 +++++++++++++++++++++++++++++++++++++++-------------- 1 files changed, 56 insertions(+), 20 deletions(-) diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c index 2db365d..0ece422 100644 --- a/hw/ppce500_pci.c +++ b/hw/ppce500_pci.c @@ -98,11 +98,20 @@ static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr) case PPCE500_PCI_OW3: case PPCE500_PCI_OW4: switch (addr & 0xC) { - case PCI_POTAR: value = pci->pob[(addr >> 5) & 0x7].potar; break; - case PCI_POTEAR: value = pci->pob[(addr >> 5) & 0x7].potear; break; - case PCI_POWBAR: value = pci->pob[(addr >> 5) & 0x7].powbar; break; - case PCI_POWAR: value = pci->pob[(addr >> 5) & 0x7].powar; break; - default: break; + case PCI_POTAR: + value = pci->pob[(addr >> 5) & 0x7].potar; + break; + case PCI_POTEAR: + value = pci->pob[(addr >> 5) & 0x7].potear; + break; + case PCI_POWBAR: + value = pci->pob[(addr >> 5) & 0x7].powbar; + break; + case PCI_POWAR: + value = pci->pob[(addr >> 5) & 0x7].powar; + break; + default: + break; } break; @@ -110,11 +119,20 @@ static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr) case PPCE500_PCI_IW2: case PPCE500_PCI_IW1: switch (addr & 0xC) { - case PCI_PITAR: value = pci->pib[(addr >> 5) & 0x3].pitar; break; - case PCI_PIWBAR: value = pci->pib[(addr >> 5) & 0x3].piwbar; break; - case PCI_PIWBEAR: value = pci->pib[(addr >> 5) & 0x3].piwbear; break; - case PCI_PIWAR: value = pci->pib[(addr >> 5) & 0x3].piwar; break; - default: break; + case PCI_PITAR: + value = pci->pib[(addr >> 5) & 0x3].pitar; + break; + case PCI_PIWBAR: + value = pci->pib[(addr >> 5) & 0x3].piwbar; + break; + case PCI_PIWBEAR: + value = pci->pib[(addr >> 5) & 0x3].piwbear; + break; + case PCI_PIWAR: + value = pci->pib[(addr >> 5) & 0x3].piwar; + break; + default: + break; }; break; @@ -154,11 +172,20 @@ static void pci_reg_write4(void *opaque, target_phys_addr_t addr, case PPCE500_PCI_OW3: case PPCE500_PCI_OW4: switch (addr & 0xC) { - case PCI_POTAR: pci->pob[(addr >> 5) & 0x7].potar = value; break; - case PCI_POTEAR: pci->pob[(addr >> 5) & 0x7].potear = value; break; - case PCI_POWBAR: pci->pob[(addr >> 5) & 0x7].powbar = value; break; - case PCI_POWAR: pci->pob[(addr >> 5) & 0x7].powar = value; break; - default: break; + case PCI_POTAR: + pci->pob[(addr >> 5) & 0x7].potar = value; + break; + case PCI_POTEAR: + pci->pob[(addr >> 5) & 0x7].potear = value; + break; + case PCI_POWBAR: + pci->pob[(addr >> 5) & 0x7].powbar = value; + break; + case PCI_POWAR: + pci->pob[(addr >> 5) & 0x7].powar = value; + break; + default: + break; }; break; @@ -166,11 +193,20 @@ static void pci_reg_write4(void *opaque, target_phys_addr_t addr, case PPCE500_PCI_IW2: case PPCE500_PCI_IW1: switch (addr & 0xC) { - case PCI_PITAR: pci->pib[(addr >> 5) & 0x3].pitar = value; break; - case PCI_PIWBAR: pci->pib[(addr >> 5) & 0x3].piwbar = value; break; - case PCI_PIWBEAR: pci->pib[(addr >> 5) & 0x3].piwbear = value; break; - case PCI_PIWAR: pci->pib[(addr >> 5) & 0x3].piwar = value; break; - default: break; + case PCI_PITAR: + pci->pib[(addr >> 5) & 0x3].pitar = value; + break; + case PCI_PIWBAR: + pci->pib[(addr >> 5) & 0x3].piwbar = value; + break; + case PCI_PIWBEAR: + pci->pib[(addr >> 5) & 0x3].piwbear = value; + break; + case PCI_PIWAR: + pci->pib[(addr >> 5) & 0x3].piwar = value; + break; + default: + break; }; break;