[2/4] ARM: tegra: Enable PLLP bypass during Tegra124 LP1
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Message ID 20191001211346.104400-2-swarren@wwwdotorg.org
State New
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Series
  • [1/4] clk: tegra: Enable fuse clock on Tegra124
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Commit Message

Stephen Warren Oct. 1, 2019, 9:13 p.m. UTC
From: Stephen Warren <swarren@nvidia.com>

For a little over a year, U-Boot has configured the flow controller to
perform automatic RAM re-repair on off->on power transitions of the CPU
rail1]. This is mandatory for correct operation of Tegra124. However, RAM
re-repair relies on certain clocks, which the kernel must enable and
leave running. PLLP is one of those clocks. This clock is shut down
during LP1 in order to save power. Enable bypass (which I believe routes
osc_div_clk, essentially the crystal clock, to the PLL output) so that
this clock signal toggles even though the PLL is not active. This is
required so that LP1 power mode (system suspend) operates correctly.

The bypass configuration must then be undone when resuming from LP1, so
that all peripheral clocks run at the expected rate. Without this, many
peripherals won't work correctly; for example, the UART baud rate would
be incorrect.

NVIDIA's downstream kernel code only does this if not compiled for
Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's
downstream code makes this change conditional upon the active CPU
cluster. The upstream kernel currently doesn't support cluster switching,
so this patch doesn't test the active CPU cluster ID.

[1] 3cc7942a4ae5 ARM: tegra: implement RAM repair

Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++
 1 file changed, 11 insertions(+)

Comments

Dmitry Osipenko Oct. 3, 2019, 11:27 a.m. UTC | #1
02.10.2019 00:13, Stephen Warren пишет:
> From: Stephen Warren <swarren@nvidia.com>
> 
> For a little over a year, U-Boot has configured the flow controller to
> perform automatic RAM re-repair on off->on power transitions of the CPU
> rail1]. This is mandatory for correct operation of Tegra124. However, RAM
> re-repair relies on certain clocks, which the kernel must enable and
> leave running. PLLP is one of those clocks. This clock is shut down
> during LP1 in order to save power. Enable bypass (which I believe routes
> osc_div_clk, essentially the crystal clock, to the PLL output) so that
> this clock signal toggles even though the PLL is not active. This is
> required so that LP1 power mode (system suspend) operates correctly.
> 
> The bypass configuration must then be undone when resuming from LP1, so
> that all peripheral clocks run at the expected rate. Without this, many
> peripherals won't work correctly; for example, the UART baud rate would
> be incorrect.
> 
> NVIDIA's downstream kernel code only does this if not compiled for
> Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's
> downstream code makes this change conditional upon the active CPU
> cluster. The upstream kernel currently doesn't support cluster switching,
> so this patch doesn't test the active CPU cluster ID.
> 
> [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair
> 
> Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
> Cc: stable@vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
>  arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
> index b408fa56eb89..6922dd8d3e2d 100644
> --- a/arch/arm/mach-tegra/sleep-tegra30.S
> +++ b/arch/arm/mach-tegra/sleep-tegra30.S
> @@ -370,6 +370,14 @@ _pll_m_c_x_done:
>  	pll_locked r1, r0, CLK_RESET_PLLC_BASE
>  	pll_locked r1, r0, CLK_RESET_PLLX_BASE
>  
> +	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
> +	cmp	r1, #TEGRA30
> +	beq	1f

What about T114, or does it need enabled PLLP as well?

> +	ldr	r1, [r0, #CLK_RESET_PLLP_BASE]
> +	bic	r1, r1, #(1<<31)	@ disable PllP bypass
> +	str	r1, [r0, #CLK_RESET_PLLP_BASE]
> +1:
> +
>  	mov32	r7, TEGRA_TMRUS_BASE
>  	ldr	r1, [r7]
>  	add	r1, r1, #LOCK_DELAY
> @@ -630,7 +638,10 @@ tegra30_switch_cpu_to_clk32k:
>  	str	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
>  
>  	/* disable PLLP, PLLA, PLLC and PLLX */
> +	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
> +	cmp	r1, #TEGRA30
>  	ldr	r0, [r5, #CLK_RESET_PLLP_BASE]
> +	orrne	r0, r0, #(1 << 31)	@ enable PllP bypass on fast cluster
>  	bic	r0, r0, #(1 << 30)
>  	str	r0, [r5, #CLK_RESET_PLLP_BASE]
>  	ldr	r0, [r5, #CLK_RESET_PLLA_BASE]
>
Stephen Warren Oct. 3, 2019, 4:34 p.m. UTC | #2
On 10/3/19 5:27 AM, Dmitry Osipenko wrote:
> 02.10.2019 00:13, Stephen Warren пишет:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> For a little over a year, U-Boot has configured the flow controller to
>> perform automatic RAM re-repair on off->on power transitions of the CPU
>> rail1]. This is mandatory for correct operation of Tegra124. However, RAM
>> re-repair relies on certain clocks, which the kernel must enable and
>> leave running. PLLP is one of those clocks. This clock is shut down
>> during LP1 in order to save power. Enable bypass (which I believe routes
>> osc_div_clk, essentially the crystal clock, to the PLL output) so that
>> this clock signal toggles even though the PLL is not active. This is
>> required so that LP1 power mode (system suspend) operates correctly.
>>
>> The bypass configuration must then be undone when resuming from LP1, so
>> that all peripheral clocks run at the expected rate. Without this, many
>> peripherals won't work correctly; for example, the UART baud rate would
>> be incorrect.
>>
>> NVIDIA's downstream kernel code only does this if not compiled for
>> Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's
>> downstream code makes this change conditional upon the active CPU
>> cluster. The upstream kernel currently doesn't support cluster switching,
>> so this patch doesn't test the active CPU cluster ID.
>>
>> [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair
>>
>> Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>> ---
>>   arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
>> index b408fa56eb89..6922dd8d3e2d 100644
>> --- a/arch/arm/mach-tegra/sleep-tegra30.S
>> +++ b/arch/arm/mach-tegra/sleep-tegra30.S
>> @@ -370,6 +370,14 @@ _pll_m_c_x_done:
>>   	pll_locked r1, r0, CLK_RESET_PLLC_BASE
>>   	pll_locked r1, r0, CLK_RESET_PLLX_BASE
>>   
>> +	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
>> +	cmp	r1, #TEGRA30
>> +	beq	1f
> 
> What about T114, or does it need enabled PLLP as well?

I'm nowhere near as familiar with T114 as T124, so I can't be 100% sure. 
However, a very quick look at the CAR section in the T114 TRM does show 
the same gate/mux structure around a reshift and fuse clock, so I assume 
the requirement is identical there.

Also, NVIDIA's downstream kernel has a compile-time ifdef around the 
code I've added here. It's not compiled for T30 specifically, and is 
compiled for anything else, which I believe means both T114 and T124.

In patch 1 in this series, I only enabled the fuse clock for T124, since 
I don't have a T114 system to test any more. However, the revised patch 
1 that Thierry and I are discussing would enable the fuse clock on all 
SoCs, and hence make the code work identically on T114 as it does on T124.
Dmitry Osipenko Oct. 3, 2019, 6 p.m. UTC | #3
03.10.2019 19:34, Stephen Warren пишет:
> On 10/3/19 5:27 AM, Dmitry Osipenko wrote:
>> 02.10.2019 00:13, Stephen Warren пишет:
>>> From: Stephen Warren <swarren@nvidia.com>
>>>
>>> For a little over a year, U-Boot has configured the flow controller to
>>> perform automatic RAM re-repair on off->on power transitions of the CPU
>>> rail1]. This is mandatory for correct operation of Tegra124. However, RAM
>>> re-repair relies on certain clocks, which the kernel must enable and
>>> leave running. PLLP is one of those clocks. This clock is shut down
>>> during LP1 in order to save power. Enable bypass (which I believe routes
>>> osc_div_clk, essentially the crystal clock, to the PLL output) so that
>>> this clock signal toggles even though the PLL is not active. This is
>>> required so that LP1 power mode (system suspend) operates correctly.
>>>
>>> The bypass configuration must then be undone when resuming from LP1, so
>>> that all peripheral clocks run at the expected rate. Without this, many
>>> peripherals won't work correctly; for example, the UART baud rate would
>>> be incorrect.
>>>
>>> NVIDIA's downstream kernel code only does this if not compiled for
>>> Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's
>>> downstream code makes this change conditional upon the active CPU
>>> cluster. The upstream kernel currently doesn't support cluster switching,
>>> so this patch doesn't test the active CPU cluster ID.
>>>
>>> [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair
>>>
>>> Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
>>> Cc: stable@vger.kernel.org
>>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>>> ---
>>>   arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++
>>>   1 file changed, 11 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
>>> index b408fa56eb89..6922dd8d3e2d 100644
>>> --- a/arch/arm/mach-tegra/sleep-tegra30.S
>>> +++ b/arch/arm/mach-tegra/sleep-tegra30.S
>>> @@ -370,6 +370,14 @@ _pll_m_c_x_done:
>>>       pll_locked r1, r0, CLK_RESET_PLLC_BASE
>>>       pll_locked r1, r0, CLK_RESET_PLLX_BASE
>>>   +    tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
>>> +    cmp    r1, #TEGRA30
>>> +    beq    1f
>>
>> What about T114, or does it need enabled PLLP as well?
> 
> I'm nowhere near as familiar with T114 as T124, so I can't be 100% sure. However, a very
> quick look at the CAR section in the T114 TRM does show the same gate/mux structure around
> a reshift and fuse clock, so I assume the requirement is identical there.

Indeed, T114 TRM suggests that it has the same requirement.

> Also, NVIDIA's downstream kernel has a compile-time ifdef around the code I've added here.
> It's not compiled for T30 specifically, and is compiled for anything else, which I believe
> means both T114 and T124.
> 
> In patch 1 in this series, I only enabled the fuse clock for T124, since I don't have a
> T114 system to test any more. However, the revised patch 1 that Thierry and I are
> discussing would enable the fuse clock on all SoCs, and hence make the code work
> identically on T114 as it does on T124.

Thanks for the clarification.

Patch
diff mbox series

diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index b408fa56eb89..6922dd8d3e2d 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -370,6 +370,14 @@  _pll_m_c_x_done:
 	pll_locked r1, r0, CLK_RESET_PLLC_BASE
 	pll_locked r1, r0, CLK_RESET_PLLX_BASE
 
+	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
+	cmp	r1, #TEGRA30
+	beq	1f
+	ldr	r1, [r0, #CLK_RESET_PLLP_BASE]
+	bic	r1, r1, #(1<<31)	@ disable PllP bypass
+	str	r1, [r0, #CLK_RESET_PLLP_BASE]
+1:
+
 	mov32	r7, TEGRA_TMRUS_BASE
 	ldr	r1, [r7]
 	add	r1, r1, #LOCK_DELAY
@@ -630,7 +638,10 @@  tegra30_switch_cpu_to_clk32k:
 	str	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
 
 	/* disable PLLP, PLLA, PLLC and PLLX */
+	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
+	cmp	r1, #TEGRA30
 	ldr	r0, [r5, #CLK_RESET_PLLP_BASE]
+	orrne	r0, r0, #(1 << 31)	@ enable PllP bypass on fast cluster
 	bic	r0, r0, #(1 << 30)
 	str	r0, [r5, #CLK_RESET_PLLP_BASE]
 	ldr	r0, [r5, #CLK_RESET_PLLA_BASE]