From patchwork Mon Sep 26 16:02:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurence Withers X-Patchwork-Id: 116933 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 51BE51007D4 for ; Thu, 29 Sep 2011 20:36:00 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 740FF284B5; Thu, 29 Sep 2011 12:35:58 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id m3ekhil9oVIH; Thu, 29 Sep 2011 12:35:58 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0596728498; Thu, 29 Sep 2011 12:35:56 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D2D7E2847D for ; Thu, 29 Sep 2011 12:35:52 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Cuf3Mv8RPDzG for ; Thu, 29 Sep 2011 12:35:51 +0200 (CEST) X-Greylist: delayed 1082 seconds by postgrey-1.27 at theia; Thu, 29 Sep 2011 12:35:49 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from chrysocolla.lwithers.me.uk (chrysocolla.lwithers.me.uk [80.68.94.184]) by theia.denx.de (Postfix) with ESMTPS id 0DF422847B for ; Thu, 29 Sep 2011 12:35:49 +0200 (CEST) Received: from 4.b.0.2.4.9.e.f.f.f.5.6.f.6.e.1.0.0.0.0.5.a.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1a5:0:1e6f:65ff:fe94:20b4] helo=rhodium.platinum.guralp.com) by chrysocolla.lwithers.me.uk with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1R9Dgr-0008UH-Lt; Thu, 29 Sep 2011 10:18:05 +0000 Received: from lwithers by rhodium.platinum.guralp.com with local (Exim 4.72) (envelope-from ) id 1R9Dgr-00053H-7g; Thu, 29 Sep 2011 10:18:05 +0000 Message-Id: In-Reply-To: References: From: Laurence Withers Date: Mon, 26 Sep 2011 16:02:30 +0000 To: u-boot@lists.denx.de Cc: Sandeep Paulraj Subject: [U-Boot] [PATCH v2] NAND: davinci: choose correct 1-bit h/w ECC reg X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de In nand_davinci_readecc(), select the correct NANDFECC register based on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC. This allows 1-bit hardware ECC to work with chip select other than CS2. Note this now matches the usage in nand_davinci_enable_hwecc(), which already had the correct handling, and allows refactoring to a single function encapsulating the register read. Without this fix, writing NAND pages to a chip not wired to CS2 would result in in the ECC calculation always returning FFFFFF for each 512-byte segment, and reading back a correctly written page (one with ECC intact) would always fail. With this fix, the ECC is written and verified correctly. Signed-off-by: Laurence Withers --- Changes for v2: Add Signed-off-by to commit message. --- drivers/mtd/nand/davinci_nand.c | 26 +++++++++++++------------- 1 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index d41579c..e8506dd 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -176,12 +176,22 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, #ifdef CONFIG_SYS_NAND_HW_ECC +static u_int32_t nand_davinci_readecc(struct mtd_info *mtd) +{ + u_int32_t ecc = 0; + + ecc = __raw_readl(&(davinci_emif_regs->nandfecc[ + CONFIG_SYS_NAND_CS - 2])); + + return ecc; +} + static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) { u_int32_t val; - (void)__raw_readl(&(davinci_emif_regs->nandfecc[ - CONFIG_SYS_NAND_CS - 2])); + /* reading the ECC result register resets the ECC calculation */ + nand_davinci_readecc(mtd); val = __raw_readl(&davinci_emif_regs->nandfcr); val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); @@ -189,22 +199,12 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) __raw_writel(val, &davinci_emif_regs->nandfcr); } -static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) -{ - u_int32_t ecc = 0; - - ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1])); - - return ecc; -} - static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { u_int32_t tmp; - const int region = 1; - tmp = nand_davinci_readecc(mtd, region); + tmp = nand_davinci_readecc(mtd); /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */