| Message ID | 20190929074239.11575-2-jagan@amarulasolutions.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | riscv: sifive/fu540: Enable SPI-NOR support | expand |
Hi Jagan, On Sun, Sep 29, 2019 at 3:42 PM Jagan Teki <jagan@amarulasolutions.com> wrote: > > Sync the hifive-unleashed-a00 dts from Linux with > below commit details: > commit 11ae2d892139a1086f257188d457ddcb71ab5257 The latest commit should be: commit c81007116bd23e9e2103c267184dc38d3acc1099 Author: Bin Meng <bmeng.cn@gmail.com> Date: Thu Sep 5 05:45:53 2019 -0700 riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes Could you use the latest one? > Author: Paul Walmsley <paul.walmsley@sifive.com> > Date: Thu Jul 25 13:41:31 2019 -0700 > > riscv: dts: fu540-c000: drop "timebase-frequency" > > Idea is to periodically sync the dts from Linux instead of > tweeking internal changes one after another, so better not typo, tweaking > add any intermediate changes in between. This would help to > maintain the dts files easy and meaningful since we are > reusing devicetree files from Linux. nits: device tree > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > --- > arch/riscv/dts/Makefile | 1 + > arch/riscv/dts/fu540-c000.dtsi | 235 ++++++++++++++++++++++++ > arch/riscv/dts/hifive-unleashed-a00.dts | 88 +++++++++ > 3 files changed, 324 insertions(+) > create mode 100644 arch/riscv/dts/fu540-c000.dtsi > create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts > Regards, Bin
On Mon, Sep 30, 2019 at 3:35 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Jagan, > > On Sun, Sep 29, 2019 at 3:42 PM Jagan Teki <jagan@amarulasolutions.com> wrote: > > > > Sync the hifive-unleashed-a00 dts from Linux with > > below commit details: > > commit 11ae2d892139a1086f257188d457ddcb71ab5257 > > The latest commit should be: > > commit c81007116bd23e9e2103c267184dc38d3acc1099 > Author: Bin Meng <bmeng.cn@gmail.com> > Date: Thu Sep 5 05:45:53 2019 -0700 > > riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes > > Could you use the latest one? Yes, will use this.
On Mon, Sep 30, 2019 at 3:35 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Jagan, > > On Sun, Sep 29, 2019 at 3:42 PM Jagan Teki <jagan@amarulasolutions.com> wrote: > > > > Sync the hifive-unleashed-a00 dts from Linux with > > below commit details: > > commit 11ae2d892139a1086f257188d457ddcb71ab5257 > > The latest commit should be: > > commit c81007116bd23e9e2103c267184dc38d3acc1099 > Author: Bin Meng <bmeng.cn@gmail.com> > Date: Thu Sep 5 05:45:53 2019 -0700 > > riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes > > Could you use the latest one? Syncing these commits other than the patch used one seems not working. SBI is failing to load u-boot-dtb.bin. I think this would some sort of cpu nodes changes on commits after riscv: dts: fu540-c000: drop "timebase-frequency"
Hi Jagan, On Sun, 2019-09-29 at 13:12 +0530, Jagan Teki wrote: > Sync the hifive-unleashed-a00 dts from Linux with > below commit details: > commit 11ae2d892139a1086f257188d457ddcb71ab5257 > Author: Paul Walmsley <paul.walmsley@sifive.com> > Date: Thu Jul 25 13:41:31 2019 -0700 > > riscv: dts: fu540-c000: drop "timebase-frequency" > > Idea is to periodically sync the dts from Linux instead of > tweeking internal changes one after another, so better not > add any intermediate changes in between. This would help to > maintain the dts files easy and meaningful since we are > reusing devicetree files from Linux. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > --- > arch/riscv/dts/Makefile | 1 + > arch/riscv/dts/fu540-c000.dtsi | 235 ++++++++++++++++++++++++ > arch/riscv/dts/hifive-unleashed-a00.dts | 88 +++++++++ > 3 files changed, 324 insertions(+) > create mode 100644 arch/riscv/dts/fu540-c000.dtsi > create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts > > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile > index f9cd606a9a..4f30e6936f 100644 > --- a/arch/riscv/dts/Makefile > +++ b/arch/riscv/dts/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0+ > > dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb > +dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb > > targets += $(dtb-y) > > diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi > new file mode 100644 > index 0000000000..42b5ec2231 > --- /dev/null > +++ b/arch/riscv/dts/fu540-c000.dtsi > @@ -0,0 +1,235 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2018-2019 SiFive, Inc */ > + > +/dts-v1/; > + > +#include <dt-bindings/clock/sifive-fu540-prci.h> > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "sifive,fu540-c000", "sifive,fu540"; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + }; > + > + chosen { > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + cpu0: cpu@0 { > + compatible = "sifive,e51", "sifive,rocket0", "riscv"; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <16384>; > + reg = <0>; > + riscv,isa = "rv64imac"; > + status = "disabled"; > + cpu0_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + cpu1: cpu@1 { > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <32>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <32>; > + mmu-type = "riscv,sv39"; > + reg = <1>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + cpu1_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + cpu2: cpu@2 { > + clock-frequency = <0>; > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <32>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <32>; > + mmu-type = "riscv,sv39"; > + reg = <2>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + cpu2_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + cpu3: cpu@3 { > + clock-frequency = <0>; > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <32>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <32>; > + mmu-type = "riscv,sv39"; > + reg = <3>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + cpu3_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + cpu4: cpu@4 { > + clock-frequency = <0>; > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <32>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <32>; > + mmu-type = "riscv,sv39"; > + reg = <4>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + cpu4_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + }; > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; > + ranges; > + plic0: interrupt-controller@c000000 { > + #interrupt-cells = <1>; > + compatible = "sifive,plic-1.0.0"; > + reg = <0x0 0xc000000 0x0 0x4000000>; > + riscv,ndev = <53>; > + interrupt-controller; > + interrupts-extended = < > + &cpu0_intc 0xffffffff > + &cpu1_intc 0xffffffff &cpu1_intc 9 > + &cpu2_intc 0xffffffff &cpu2_intc 9 > + &cpu3_intc 0xffffffff &cpu3_intc 9 > + &cpu4_intc 0xffffffff &cpu4_intc 9>; > + }; > + prci: clock-controller@10000000 { > + compatible = "sifive,fu540-c000-prci"; > + reg = <0x0 0x10000000 0x0 0x1000>; > + clocks = <&hfclk>, <&rtcclk>; > + #clock-cells = <1>; > + }; > + uart0: serial@10010000 { > + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; > + reg = <0x0 0x10010000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <4>; > + clocks = <&prci PRCI_CLK_TLCLK>; > + status = "disabled"; > + }; > + uart1: serial@10011000 { > + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; > + reg = <0x0 0x10011000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <5>; > + clocks = <&prci PRCI_CLK_TLCLK>; > + status = "disabled"; > + }; > + i2c0: i2c@10030000 { > + compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; > + reg = <0x0 0x10030000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <50>; > + clocks = <&prci PRCI_CLK_TLCLK>; > + reg-shift = <2>; > + reg-io-width = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + qspi0: spi@10040000 { > + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; > + reg = <0x0 0x10040000 0x0 0x1000 > + 0x0 0x20000000 0x0 0x10000000>; > + interrupt-parent = <&plic0>; > + interrupts = <51>; > + clocks = <&prci PRCI_CLK_TLCLK>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + qspi1: spi@10041000 { > + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; > + reg = <0x0 0x10041000 0x0 0x1000 > + 0x0 0x30000000 0x0 0x10000000>; > + interrupt-parent = <&plic0>; > + interrupts = <52>; > + clocks = <&prci PRCI_CLK_TLCLK>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + qspi2: spi@10050000 { > + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; > + reg = <0x0 0x10050000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <6>; > + clocks = <&prci PRCI_CLK_TLCLK>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + eth0: ethernet@10090000 { > + compatible = "sifive,fu540-c000-gem"; > + interrupt-parent = <&plic0>; > + interrupts = <53>; > + reg = <0x0 0x10090000 0x0 0x2000 > + 0x0 0x100a0000 0x0 0x1000>; > + local-mac-address = [00 00 00 00 00 00]; > + clock-names = "pclk", "hclk"; > + clocks = <&prci PRCI_CLK_GEMGXLPLL>, > + <&prci PRCI_CLK_GEMGXLPLL>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + }; > +}; > diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts > new file mode 100644 > index 0000000000..7397b740b4 > --- /dev/null > +++ b/arch/riscv/dts/hifive-unleashed-a00.dts > @@ -0,0 +1,88 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2018-2019 SiFive, Inc */ > + > +#include "fu540-c000.dtsi" > + > +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ > +#define RTCCLK_FREQ 1000000 > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + model = "SiFive HiFive Unleashed A00"; > + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; > + > + chosen { > + stdout-path = "/soc/serial@10010000:115200"; This is not part of the upstream Linux device tree, so it is probably better to put it into hifive-unleashed-a00-u-boot.dtsi. Thanks, Lukas > + }; > + > + cpus { > + timebase-frequency = <RTCCLK_FREQ>; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x0 0x80000000 0x2 0x00000000>; > + }; > + > + soc { > + }; > + > + hfclk: hfclk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <33333333>; > + clock-output-names = "hfclk"; > + }; > + > + rtcclk: rtcclk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <RTCCLK_FREQ>; > + clock-output-names = "rtcclk"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > + > +&uart1 { > + status = "okay"; > +}; > + > +&i2c0 { > + status = "okay"; > +}; > + > +&qspi0 { > + status = "okay"; > + flash@0 { > + compatible = "issi,is25wp256", "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <50000000>; > + m25p,fast-read; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > + }; > +}; > + > +&qspi2 { > + status = "okay"; > + mmc@0 { > + compatible = "mmc-spi-slot"; > + reg = <0>; > + spi-max-frequency = <20000000>; > + voltage-ranges = <3300 3300>; > + disable-wp; > + }; > +}; > + > +ð0 { > + status = "okay"; > + phy-mode = "gmii"; > + phy-handle = <&phy0>; > + phy0: ethernet-phy@0 { > + reg = <0>; > + }; > +};
Hi Jagan, On Wed, 2019-10-02 at 15:57 +0530, Jagan Teki wrote: > On Mon, Sep 30, 2019 at 3:35 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Jagan, > > > > On Sun, Sep 29, 2019 at 3:42 PM Jagan Teki <jagan@amarulasolutions.com> wrote: > > > Sync the hifive-unleashed-a00 dts from Linux with > > > below commit details: > > > commit 11ae2d892139a1086f257188d457ddcb71ab5257 > > > > The latest commit should be: > > > > commit c81007116bd23e9e2103c267184dc38d3acc1099 > > Author: Bin Meng <bmeng.cn@gmail.com> > > Date: Thu Sep 5 05:45:53 2019 -0700 > > > > riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes > > > > Could you use the latest one? > > Syncing these commits other than the patch used one seems not working. > SBI is failing to load u-boot-dtb.bin. I think this would some sort of > cpu nodes changes on commits after > riscv: dts: fu540-c000: drop "timebase-frequency" I just tried it with the device tree from the commit Bin referred to and did not have any problems starting U-Boot. Are you perhaps only missing chosen/stdout-path? Thanks, Lukas
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index f9cd606a9a..4f30e6936f 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb targets += $(dtb-y) diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi new file mode 100644 index 0000000000..42b5ec2231 --- /dev/null +++ b/arch/riscv/dts/fu540-c000.dtsi @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +#include <dt-bindings/clock/sifive-fu540-prci.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <53>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <4>; + clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <5>; + clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <50>; + clocks = <&prci PRCI_CLK_TLCLK>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <51>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi2: spi@10050000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <6>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@10090000 { + compatible = "sifive,fu540-c000-gem"; + interrupt-parent = <&plic0>; + interrupts = <53>; + reg = <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address = [00 00 00 00 00 00]; + clock-names = "pclk", "hclk"; + clocks = <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + }; +}; diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts new file mode 100644 index 0000000000..7397b740b4 --- /dev/null +++ b/arch/riscv/dts/hifive-unleashed-a00.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +#include "fu540-c000.dtsi" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + stdout-path = "/soc/serial@10010000:115200"; + }; + + cpus { + timebase-frequency = <RTCCLK_FREQ>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <RTCCLK_FREQ>; + clock-output-names = "rtcclk"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&qspi0 { + status = "okay"; + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +};
Sync the hifive-unleashed-a00 dts from Linux with below commit details: commit 11ae2d892139a1086f257188d457ddcb71ab5257 Author: Paul Walmsley <paul.walmsley@sifive.com> Date: Thu Jul 25 13:41:31 2019 -0700 riscv: dts: fu540-c000: drop "timebase-frequency" Idea is to periodically sync the dts from Linux instead of tweeking internal changes one after another, so better not add any intermediate changes in between. This would help to maintain the dts files easy and meaningful since we are reusing devicetree files from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/fu540-c000.dtsi | 235 ++++++++++++++++++++++++ arch/riscv/dts/hifive-unleashed-a00.dts | 88 +++++++++ 3 files changed, 324 insertions(+) create mode 100644 arch/riscv/dts/fu540-c000.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts