From patchwork Wed Sep 28 19:52:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jana Rapava X-Patchwork-Id: 116850 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 169BCB6F86 for ; Thu, 29 Sep 2011 05:49:39 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C1A9728381; Wed, 28 Sep 2011 21:49:37 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FqR3izC+5h5l; Wed, 28 Sep 2011 21:49:37 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BA54E282DE; Wed, 28 Sep 2011 21:49:34 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 83004282DE for ; Wed, 28 Sep 2011 21:49:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2m6XnMe01J26 for ; Wed, 28 Sep 2011 21:49:29 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-fx0-f44.google.com (mail-fx0-f44.google.com [209.85.161.44]) by theia.denx.de (Postfix) with ESMTPS id 3BE67282B9 for ; Wed, 28 Sep 2011 21:49:27 +0200 (CEST) Received: by fxd18 with SMTP id 18so896894fxd.3 for ; Wed, 28 Sep 2011 12:49:27 -0700 (PDT) Received: by 10.223.34.70 with SMTP id k6mr14866413fad.31.1317239366901; Wed, 28 Sep 2011 12:49:26 -0700 (PDT) Received: from hex.kolej.mff.cuni.cz (janalaptop.kolej.mff.cuni.cz. [78.128.199.214]) by mx.google.com with ESMTPS id c5sm28493714fai.2.2011.09.28.12.49.26 (version=SSLv3 cipher=OTHER); Wed, 28 Sep 2011 12:49:26 -0700 (PDT) From: Jana Rapava To: u-boot@lists.denx.de Date: Wed, 28 Sep 2011 21:52:43 +0200 Message-Id: <1317239563-32311-1-git-send-email-fermata7@gmail.com> X-Mailer: git-send-email 1.7.6.3 In-Reply-To: <1317239475-32265-1-git-send-email-fermata7@gmail.com> References: <1317239475-32265-1-git-send-email-fermata7@gmail.com> Cc: Jana Rapava Subject: [U-Boot] [PATCH v9 3/4] EHCI: adjust for mx5 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add macros and structures needed by Efika USB support code. Move shared offset and bits definitions into common header file. Signed-off-by: Jana Rapava Cc: Marek Vasut Cc: Remy Bohmer Cc: Stefano Babic --- Changes for v1: - split into patchset Changes for v2: - make this the third patch in series - move all #define's from ehci-mxc.c to ehci-fsl.h - rename structures Changes for v3: - rebase on top of u-boot-imx/next (no actual changes) Changes for v4: - no changes - change changelog versioning from per patchset to per patch Changes for v5: - whitespace changes (no actual changes) Changes for v6: - no changes drivers/usb/host/ehci-mxc.c | 31 +-------- include/usb/ehci-fsl.h | 146 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 148 insertions(+), 29 deletions(-) diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index fde1f0f..2c1295f 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -27,31 +27,6 @@ #include #include -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#ifdef CONFIG_MX25 -#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6) -#define MX25_USB_CTRL_HSTD_BIT (1<<5) -#define MX25_USB_CTRL_USBTE_BIT (1<<4) -#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3) -#endif - -#ifdef CONFIG_MX31 -#define MX31_OTG_SIC_SHIFT 29 -#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) -#define MX31_OTG_PM_BIT (1 << 24) - -#define MX31_H2_SIC_SHIFT 21 -#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) -#define MX31_H2_PM_BIT (1 << 16) -#define MX31_H2_DT_BIT (1 << 5) - -#define MX31_H1_SIC_SHIFT 13 -#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) -#define MX31_H1_PM_BIT (1 << 8) -#define MX31_H1_DT_BIT (1 << 4) -#endif - static int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; @@ -66,11 +41,11 @@ static int mxc_set_usbcontrol(int port, unsigned int flags) switch (port) { case 0: /* OTG port */ - v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); + v &= ~(MXC_OTG_SIC_MASK | MXC_OTG_PM_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX31_OTG_SIC_SHIFT; + << MXC_OTG_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_OTG_PM_BIT; + v |= MXC_OTG_PM_BIT; break; case 1: /* H1 port */ diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index 67600ed..727134f 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -169,6 +169,106 @@ #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR #endif +#if defined(CONFIG_MX25) || defined(CONFIG_MX31) +#define USBCTRL_OTGBASE_OFFSET 0x600 +#endif + +#ifdef CONFIG_MX25 +#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6) +#define MX25_USB_CTRL_HSTD_BIT (1<<5) +#define MX25_USB_CTRL_USBTE_BIT (1<<4) +#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3) +#endif + +#ifdef CONFIG_MX31 +#define MX31_H2_SIC_SHIFT 21 +#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) +#define MX31_H2_PM_BIT (1 << 16) +#define MX31_H2_DT_BIT (1 << 5) + +#define MX31_H1_SIC_SHIFT 13 +#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) +#define MX31_H1_PM_BIT (1 << 8) +#define MX31_H1_DT_BIT (1 << 4) +#endif + +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) +/* offset for first USB CTRL register */ +#define MX5_CTRL_REGS_OFFSET 0x800 +#endif + +#if defined(CONFIG_MX51) || defined(CONFIG_MX31) +/* USB_CTRL register bits of interest*/ +#define MXC_OTG_SIC_SHIFT 29 +#define MXC_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) +#define MXC_OTG_WUE (1 << 27) +#define MXC_OTG_PM (1 << 24) +#endif + +#ifdef CONFIG_MX51 +#define MX51_REGISTER_LAYOUT_LENGTH 0x200 + +/* Register offsets for MX51 */ +#define MX51_OTG_ID 0x000 +#define MX51_UH1_ID 0x200 +#define MX51_UH2_ID 0x400 + +/* USB_CTRL register bits of interest*/ +#define MX51_OTG_PM (1 << 24) +#define MX51_H1_ULPI_IE (1 << 12) +#define MX51_H1_WUE (1 << 11) +#define MX51_H1_PM (1 << 8) + +/* PHY_CTRL_0 register bits of interest */ +#define MX51_OTG_OVERCURD (1 << 8) +#define MX51_EHCI_POWERPINSE (1 << 5) + +/* PHY_CTRL_1 register bits of interest */ +#define MX51_SYSCLOCK_24_MHZ (1 << 0) +#define MX51_SYSCLOCK_MASK (~(0xffffffff << 2)) + +/* USB_CTRL_1 register bits of interest */ +#define MX51_H1_EXTCLKE (1 << 25) + +/* USB Host 2 CTRL register bits of interest */ +#define MX51_H2_ULPI_IE (1 << 8) +#define MX51_H2_WUE (1 << 7) +#define MX51_H2_PM (1 << 4) + +/* PORTSCx bits of interest */ +#define MX51_ULPI_MODE_MASK (2 << 30) +#define MX51_16BIT_UTMI (1 << 28) + +/* USBCMD bits of interest */ +#define MX51_ITC_IMMEDIATE_MASK (0xff << 16) +#endif + +/* +* ULPI +*/ +#define ULPI_ID_REGS_COUNT 4 +#define ULPI_TEST_VALUE 0x55 +#define ULPI_TIMEOUT 1000 /* some reasonable value */ + +/* ULPI viewport control bits */ +#define ULPI_WU (1 << 31) +#define ULPI_SS (1 << 27) +#define ULPI_RWRUN (1 << 30) +#define ULPI_RWCTRL (1 << 29) + +/* ULPI OTG Control bits of interest */ +#define ULPI_OTG_EXT_VBUS_IND (1 << 7) +#define ULPI_OTG_DM_PULLDOWN (1 << 2) +#define ULPI_OTG_DP_PULLDOWN (1 << 1) +#define ULPI_OTG_DRV_VBUS (1 << 5) +#define ULPI_OTG_DRV_VBUS_EXT (1 << 6) +#define ULPI_OTG_CHRG_VBUS (1 << 4) + +/* ULPI Function Control bits of interest */ +#define ULPI_FC_XCVR_SELECT (1 << 0) +#define ULPI_FC_OPMODE_NORMAL (0 << 3) +#define ULPI_FC_SUSPENDM_PWRED (1 << 6) + /* * USB Registers */ @@ -210,7 +310,7 @@ struct usb_ehci { u32 txfilltuning; /* 0x164 - Host TT Transmit pre-buffer packet tuning */ u8 res7[0x8]; - u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */ + u32 ulpi_viewpoint; /* 0x170 - ULPI Register Access */ u8 res8[0xc]; u32 config_flag; /* 0x180 - Configured Flag Register */ u32 portsc; /* 0x184 - Port status/control */ @@ -242,4 +342,48 @@ struct usb_ehci { u8 res13[0xafc]; }; +struct mx5_usb_control_regs { + u32 usbctrl; /* 0x800 - USB Control */ + u32 otgmirror; /* 0x804 - OTG Port Mirror */ + u32 phyctrl0; /* 0x808 - UTMI PHY Control Register 0 */ + u32 phyctrl1; /* 0x80C - UTMI PHY Control Register 1 */ + u32 usbctrl1; /* 0x810 - USB Control Register 1 */ + u32 uh2ctrl; /* 0x814 - USB Host2 Control */ + u32 uh3ctrl; /* 0x818 - USB Host3 Control */ +}; + +struct mxc_ulpi_regs { + u8 vendor_id_low; /* 0x00 - Vendor ID lower byte */ + u8 vendor_id_high; /* 0x01 - Vendor ID upper byte */ + u8 product_id_low; /* 0x02 - Product ID lower byte */ + u8 product_id_high; /* 0x03 - Product ID higher byte */ + /* Function Control; 0x04 - 0x06 Read, 0x04 Write */ + u8 function_ctrl_write; + u8 function_ctrl_set; /* 0x05 Set */ + u8 function_ctrl_clear; /* 0x06 Clear */ + /* Interface Control; 0x07 - 0x09 Read, 0x07 Write */ + u8 iface_ctrl_write; + u8 iface_ctrl_set; /* 0x08 Set */ + u8 iface_ctrl_clear; /* 0x09 Clear */ + /* OTG Control; 0x0A - 0x0C Read, 0x0A Write */ + u8 otg_ctrl_write; + u8 otg_ctrl_set; /* 0x0B Set */ + u8 otg_ctrl_clear; /* 0x0C Clear */ + /* USB Interrupt Enable Rising; 0x0D - 0x0F Read, 0x0D Write */ + u8 usb_ie_rising_write; + u8 usb_ie_rising_set; /* 0x0E Set */ + u8 usb_ie_rising_clear; /* 0x0F Clear */ + /* USB Interrupt Enable Falling; 0x10 - 0x12 Read, 0x10 Write */ + u8 usb_ie_falling_write; + u8 usb_ie_falling_set; /* 0x11 Set */ + u8 usb_ie_falling_clear; /* 0x12 Clear */ + u8 usb_int_status; /* 0x13 - USB Interrupt Status */ + u8 usb_int_latch; /* 0x14 - USB Interrupt Latch */ + u8 debug; /* 0x15 - Debug */ + /* Scratch Register; 0x16 - 0x18 Read, 0x16 Write */ + u8 scratch_write; + u8 scratch_set; /* 0x17 Set */ + u8 scratch_clear; /* 0x18 Clear*/ +}; + #endif /* _EHCI_FSL_H */