From patchwork Wed Sep 28 14:34:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Clifton X-Patchwork-Id: 116797 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id E9CB3B6F62 for ; Thu, 29 Sep 2011 00:33:04 +1000 (EST) Received: (qmail 22739 invoked by alias); 28 Sep 2011 14:33:03 -0000 Received: (qmail 22697 invoked by uid 22791); 28 Sep 2011 14:33:01 -0000 X-SWARE-Spam-Status: No, hits=-6.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, SPF_HELO_PASS X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 28 Sep 2011 14:32:44 +0000 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p8SEWiSw030979 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Wed, 28 Sep 2011 10:32:44 -0400 Received: from Gift.redhat.com (vpn1-6-144.ams2.redhat.com [10.36.6.144]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id p8SEWgde019169 for ; Wed, 28 Sep 2011 10:32:43 -0400 From: Nick Clifton To: gcc-patches@gcc.gnu.org Subject: Commit: RX: Add support for MIN and MAX instructions in QI and HI modes Date: Wed, 28 Sep 2011 15:34:25 +0100 Message-ID: MIME-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi Guys, I am going to apply the patch below to the RX backend to add support for generating MIN and MAX instructions for HI and QI modes. Cheers Nick gcc/ChangeLog 2011-09-28 Nick Clifton * config/rx/predicates.md (rx_minmax_operand): New predicate. Accepts immediates and a restricted subset of MEMs. * config/rx/rx.md (int_modes): New iterator. (smaxsi3, sminsi3): Delete and replace with... (smax3, smin3): New patterns. (umax<>3_u, umax<>3_ur, umax<>3, umin<>3): New patterns. Index: gcc/config/rx/predicates.md =================================================================== --- gcc/config/rx/predicates.md (revision 179307) +++ gcc/config/rx/predicates.md (working copy) @@ -72,6 +72,16 @@ (match_operand 0 "rx_restricted_mem_operand")) ) +;; Check that the operand is suitable as the source operand +;; for a min/max instruction. This is the same as +;; rx_source_operand except that CONST_INTs are allowed but +;; REGs and SUBREGs are not. + +(define_predicate "rx_minmaxex_operand" + (ior (match_operand 0 "immediate_operand") + (match_operand 0 "rx_restricted_mem_operand")) +) + ;; Return true if OP is a store multiple operation. This looks like: ;; ;; [(set (SP) (MINUS (SP) (INT))) Index: gcc/config/rx/rx.md =================================================================== --- gcc/config/rx/rx.md (revision 179307) +++ gcc/config/rx/rx.md (working copy) @@ -22,6 +22,9 @@ ;; This code iterator is used for sign- and zero- extensions. (define_mode_iterator small_int_modes [(HI "") (QI "")]) +;; This code iterator is used for max and min operations. +(define_mode_iterator int_modes [(SI "") (HI "") (QI "")]) + ;; We do not handle DFmode here because it is either ;; the same as SFmode, or if -m64bit-doubles is active ;; then all operations on doubles have to be handled by @@ -1160,28 +1163,109 @@ (set_attr "timings" "22,44")] ) -(define_insn "smaxsi3" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") - (smax:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0") - (match_operand:SI 2 "rx_source_operand" - "r,Sint08,Sint16,Sint24,i,Q")))] +(define_insn "smax3" + [(set (match_operand:int_modes 0 "register_operand" "=r,r,r,r,r,r") + (smax:int_modes (match_operand:int_modes 1 "register_operand" "%0,0,0,0,0,0") + (match_operand:int_modes 2 "rx_source_operand" + "r,Sint08,Sint16,Sint24,i,Q")))] "" "max\t%Q2, %0" [(set_attr "length" "3,4,5,6,7,6") (set_attr "timings" "11,11,11,11,11,33")] ) -(define_insn "sminsi3" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") - (smin:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0") - (match_operand:SI 2 "rx_source_operand" - "r,Sint08,Sint16,Sint24,i,Q")))] +(define_insn "smin3" + [(set (match_operand:int_modes 0 "register_operand" "=r,r,r,r,r,r") + (smin:int_modes (match_operand:int_modes 1 "register_operand" "%0,0,0,0,0,0") + (match_operand:int_modes 2 "rx_source_operand" + "r,Sint08,Sint16,Sint24,i,Q")))] "" "min\t%Q2, %0" [(set_attr "length" "3,4,5,6,7,6") (set_attr "timings" "11,11,11,11,11,33")] ) +(define_insn "umax3_u" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") + (smax:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0") + (zero_extend:SI (match_operand:small_int_modes 2 "rx_minmaxex_operand" + "r,Sint08,Sint16,Sint24,i,Q"))))] + "" + "max\t%R2, %0" + [(set_attr "length" "3,4,5,6,7,6") + (set_attr "timings" "11,11,11,11,11,33")] +) + +(define_insn "umin3_ur" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") + (smin:SI (zero_extend:SI (match_operand:small_int_modes 2 "rx_minmaxex_operand" + "r,Sint08,Sint16,Sint24,i,Q")) + (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")))] + "" + "min\t%R2, %0" + [(set_attr "length" "3,4,5,6,7,6") + (set_attr "timings" "11,11,11,11,11,33")] +) + +(define_insn "umax3_ur" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") + (smax:SI (zero_extend:SI (match_operand:small_int_modes 2 "rx_minmaxex_operand" + "r,Sint08,Sint16,Sint24,i,Q")) + (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")))] + "" + "max\t%R2, %0" + [(set_attr "length" "3,4,5,6,7,6") + (set_attr "timings" "11,11,11,11,11,33")] +) + +(define_expand "umax3" + [(set (match_dup 4) + (zero_extend:SI (match_operand:small_int_modes 1 "register_operand" "%0,0,0,0,0,0"))) + (set (match_dup 3) + (smax:SI (match_dup 4) + (match_operand:small_int_modes 2 "rx_source_operand" + "r,Sint08,Sint16,Sint24,i,Q"))) + (set (match_operand:small_int_modes 0 "register_operand" "=r,r,r,r,r,r") + (match_dup 6)) + ] + "" + "operands[3] = gen_reg_rtx (SImode); + operands[4] = gen_reg_rtx (SImode); + operands[5] = gen_reg_rtx (SImode); + operands[6] = gen_rtx_SUBREG (GET_MODE (operands[0]), operands[3], + TARGET_BIG_ENDIAN_DATA ? (GET_MODE (operands[0]) == HImode ? 2 : 3) : 0); + if (GET_CODE (operands[2]) != CONST_INT) + { + emit_move_insn (operands[5], gen_rtx_ZERO_EXTEND (SImode, operands[2])); + operands[2] = operands[5]; + } + " +) + +(define_expand "umin3" + [(set (match_dup 4) + (zero_extend:SI (match_operand:small_int_modes 1 "register_operand" "%0,0,0,0,0,0"))) + (set (match_dup 3) + (smin:SI (match_dup 4) + (match_operand:small_int_modes 2 "rx_source_operand" + "r,Sint08,Sint16,Sint24,i,Q"))) + (set (match_operand:small_int_modes 0 "register_operand" "=r,r,r,r,r,r") + (match_dup 6)) + ] + "" + "operands[3] = gen_reg_rtx (SImode); + operands[4] = gen_reg_rtx (SImode); + operands[5] = gen_reg_rtx (SImode); + operands[6] = gen_rtx_SUBREG (GET_MODE (operands[0]), operands[3], + TARGET_BIG_ENDIAN_DATA ? (GET_MODE (operands[0]) == HImode ? 2 : 3) : 0); + if (GET_CODE (operands[2]) != CONST_INT) + { + emit_move_insn (operands[5], gen_rtx_ZERO_EXTEND (SImode, operands[2])); + operands[2] = operands[5]; + } + " +) + (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") (mult:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r")