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b=OfEpwMbAKXCZV9mOhZyelpWVAotPqN+1yZOQF8OKkMhjtYUIJ4NVnwK2AGUjCt5Q/izfYow8Mu1GY2tEuLL1GyJX1NWHDqFxFhM6GhvJPOQBG5JJy2TZZQ1awafQVnVBwPAhKOr1P7/8gfSLqD1Z88n2HohMTSXAVALjTlSJRbY= Received: from MN2PR11MB4448.namprd11.prod.outlook.com (52.135.39.157) by MN2PR11MB4319.namprd11.prod.outlook.com (52.135.39.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2284.26; Tue, 24 Sep 2019 07:46:41 +0000 Received: from MN2PR11MB4448.namprd11.prod.outlook.com ([fe80::c951:b15a:e4b3:30f7]) by MN2PR11MB4448.namprd11.prod.outlook.com ([fe80::c951:b15a:e4b3:30f7%7]) with mapi id 15.20.2284.023; Tue, 24 Sep 2019 07:46:41 +0000 From: To: , , , , , Subject: [PATCH v2 15/22] mtd: spi-nor: Drop spansion_quad_enable() Thread-Topic: [PATCH v2 15/22] mtd: spi-nor: Drop spansion_quad_enable() Thread-Index: AQHVcqw0rTwdPSINzEqLofiTPWzT3g== Date: Tue, 24 Sep 2019 07:46:41 +0000 Message-ID: <20190924074533.6618-16-tudor.ambarus@microchip.com> References: <20190924074533.6618-1-tudor.ambarus@microchip.com> In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR0101CA0082.eurprd01.prod.exchangelabs.com (2603:10a6:800:1f::50) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 72065e81-89bf-45a3-5090-08d740c3568b x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600167)(711020)(4605104)(1401327)(2017052603328)(7193020); SRVR:MN2PR11MB4319; x-ms-traffictypediagnostic: MN2PR11MB4319: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-forefront-prvs: 0170DAF08C x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(1496009)(366004)(396003)(136003)(346002)(39860400002)(376002)(189003)(199004)(5660300002)(2201001)(6436002)(256004)(86362001)(11346002)(14454004)(476003)(2501003)(305945005)(186003)(2616005)(26005)(386003)(102836004)(6506007)(25786009)(6486002)(8936002)(81156014)(2906002)(3846002)(81166006)(107886003)(7736002)(8676002)(6512007)(486006)(36756003)(52116002)(71200400001)(71190400001)(50226002)(446003)(66446008)(76176011)(99286004)(66946007)(4326008)(66476007)(64756008)(66556008)(6116002)(54906003)(110136005)(66066001)(316002)(1076003)(7416002)(478600001); DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR11MB4319; H:MN2PR11MB4448.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Hogk0Fm8KMi6Gm8VDNWXePPMcEGZA8En4kiNQHUMZRCxRQHVcmK6xXJCXW67mYIlvGD5yxuC8alICDMReCRevKQym+tvU0sByEVUcyJx0LtE7J/hGGMbX7H75AJp4uzVsWIoJ1mpQ+/KjjPWlFFcm1Haev3R7w8GJ4TOLW31VWlyPQJp8ZL1vXwM/xFXAqYf5UWIccgcNDbIjY/N793PI6ekDyMMEqV4+fp48FYx4B2QM6JLvjqMk2iorVJXP4OJCZSk1A88DRlK0mlJFiKQHpWOeC3qMK91N+sLoJKZN7ci0UVCzy9SaihCRFVjfUStL0kMUinrW47SBBfQTA3TWJ9/qvDOhlTLAf5srXiIGJ1/xc48F+Y8CFFjwB5Ic/HK47Vtl47xeLEcMYmdB1gT8syUs6+DQUmT1SzpLD3NtcI= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 72065e81-89bf-45a3-5090-08d740c3568b X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Sep 2019 07:46:41.2934 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4ah3Qr5TuC6ktDmrY693eqvIJBHABCOEdo4bzeITxHxxECo8zGlzpZWGdvjkXLlbLrBua20RW4H8nxudmSxT/ZR+eIBj6T7NZpjPCm3jz3o= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4319 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-aspeed@lists.ozlabs.org, Tudor.Ambarus@microchip.com, richard@nod.at, linux-kernel@vger.kernel.org, vz@mleia.com, linux-mediatek@lists.infradead.org, miquel.raynal@bootlin.com, matthias.bgg@gmail.com, computersforpeace@gmail.com, dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" From: Tudor Ambarus Drop the default spansion_quad_enable() method and replace it with spansion_read_cr_quad_enable(). The function was buggy, it didn't care about the previous values of the Status and Configuration Registers. spansion_read_cr_quad_enable() is a Read-Modify-Write-Check function that keeps track of what were the previous values of the Status and Configuration Registers. In terms of instruction types sent to the flash, the only difference between the spansion_quad_enable() and spansion_read_cr_quad_enable() is that the later calls spi_nor_read_sr(). We can safely assume that all flashes support spi_nor_read_sr(), because all flashes call it in spi_nor_sr_ready(). The transition from spansion_quad_enable() to spansion_read_cr_quad_enable() will not affect anybody, drop the buggy code. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 58 ++++--------------------------------------- 1 file changed, 5 insertions(+), 53 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index d971f5a4b11f..668afa9a8c87 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1869,54 +1869,6 @@ static int macronix_quad_enable(struct spi_nor *nor) } /** - * spansion_quad_enable() - set QE bit in Configuraiton Register. - * @nor: pointer to a 'struct spi_nor' - * - * Set the Quad Enable (QE) bit in the Configuration Register. - * This function is kept for legacy purpose because it has been used for a - * long time without anybody complaining but it should be considered as - * deprecated and maybe buggy. - * First, this function doesn't care about the previous values of the Status - * and Configuration Registers when it sets the QE bit (bit 1) in the - * Configuration Register: all other bits are cleared, which may have unwanted - * side effects like removing some block protections. - * Secondly, it uses the Read Configuration Register (35h) instruction though - * some very old and few memories don't support this instruction. If a pull-up - * resistor is present on the MISO/IO1 line, we might still be able to pass the - * "read back" test because the QSPI memory doesn't recognize the command, - * so leaves the MISO/IO1 line state unchanged, hence spi_nor_read_cr(nor, cr) - * gets the 0xFF value. - * - * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI - * memories. - * - * Return: 0 on success, -errno otherwise. - */ -static int spansion_quad_enable(struct spi_nor *nor) -{ - u8 *sr_cr = nor->bouncebuf; - int ret; - - sr_cr[0] = 0; - sr_cr[1] = CR_QUAD_EN_SPAN; - ret = spi_nor_write_sr(nor, sr_cr, 2); - if (ret) - return ret; - - /* read back and check it */ - ret = spi_nor_read_cr(nor, &nor->bouncebuf[0]); - if (ret) - return ret; - - if (!(nor->bouncebuf[0] & CR_QUAD_EN_SPAN)) { - dev_err(nor->dev, "Spansion Quad bit not set\n"); - return -EINVAL; - } - - return 0; -} - -/** * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register. * @nor: pointer to a 'struct spi_nor' * @@ -2071,9 +2023,9 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) * * Read-modify-write function that clears the Block Protection bits from the * Status Register without affecting other bits. The function is tightly - * coupled with the spansion_quad_enable() function. Both assume that the Write - * Register with 16 bits, together with the Read Configuration Register (35h) - * instructions are supported. + * coupled with the spansion_read_cr_quad_enable() function. Both assume that + * the Write Register with 16 bits, together with the Read Configuration + * Register (35h) instructions are supported. * * Return: 0 on success, -errno otherwise. */ @@ -4560,7 +4512,7 @@ static void spi_nor_info_init_flash_params(struct spi_nor *nor) u8 i, erase_mask; /* Initialize legacy flash parameters and settings. */ - flash->quad_enable = spansion_quad_enable; + flash->quad_enable = spansion_read_cr_quad_enable; flash->set_4byte = spansion_set_4byte; flash->setup = spi_nor_default_setup; @@ -4776,7 +4728,7 @@ static int spi_nor_init(struct spi_nor *nor) int err; if (nor->clear_sr_bp) { - if (nor->flash.quad_enable == spansion_quad_enable) + if (nor->flash.quad_enable == spansion_read_cr_quad_enable) nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp; err = nor->clear_sr_bp(nor);