diff mbox series

[rs6000] Fix non-canonical CONST_INTs in altivec_copysign_v4sf3 (PR91823)

Message ID mptef07s5lp.fsf@arm.com
State New
Headers show
Series [rs6000] Fix non-canonical CONST_INTs in altivec_copysign_v4sf3 (PR91823) | expand

Commit Message

Richard Sandiford Sept. 23, 2019, 9:51 a.m. UTC 
The pattern was generating zero-extended rather than sign-extended
CONST_INTs.

Tested by Bill Seurer (thanks!).  OK to install?

Richard


2019-09-23  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR target/91823
	* config/rs6000/altivec.md (altivec_copysign_v4sf3): Generate
	canonical CONST_INTs.  Use gen_rtvec_v.

Comments

Segher Boessenkool Sept. 23, 2019, 11:24 a.m. UTC | #1 
On Mon, Sep 23, 2019 at 10:51:30AM +0100, Richard Sandiford wrote:
> The pattern was generating zero-extended rather than sign-extended
> CONST_INTs.
> 
> Tested by Bill Seurer (thanks!).  OK to install?

Sure!  One nit:

> gcc/
> 	PR target/91823
> 	* config/rs6000/altivec.md (altivec_copysign_v4sf3): Generate
> 	canonical CONST_INTs.  Use gen_rtvec_v.

You actually use gen_rtvec here.

Okay for trunk (and backports if you want those).  Thanks!


Segher
diff mbox series

Patch

Index: gcc/config/rs6000/altivec.md
===================================================================
--- gcc/config/rs6000/altivec.md	2019-08-25 19:10:35.582156848 +0100
+++ gcc/config/rs6000/altivec.md	2019-09-23 10:48:21.998225836 +0100
@@ -2198,13 +2198,8 @@  (define_expand "altivec_copysign_v4sf3"
   "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
 {
   rtx mask = gen_reg_rtx (V4SImode);
-  rtvec v = rtvec_alloc (4);
-  unsigned HOST_WIDE_INT mask_val = ((unsigned HOST_WIDE_INT)1) << 31;
-
-  RTVEC_ELT (v, 0) = GEN_INT (mask_val);
-  RTVEC_ELT (v, 1) = GEN_INT (mask_val);
-  RTVEC_ELT (v, 2) = GEN_INT (mask_val);
-  RTVEC_ELT (v, 3) = GEN_INT (mask_val);
+  rtx mask_val = gen_int_mode (HOST_WIDE_INT_1U << 31, SImode);
+  rtvec v = gen_rtvec (4, mask_val, mask_val, mask_val, mask_val);
 
   emit_insn (gen_vec_initv4sisi (mask, gen_rtx_PARALLEL (V4SImode, v)));
   emit_insn (gen_vector_select_v4sf (operands[0], operands[1], operands[2],