From patchwork Mon Sep 26 15:10:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?=C5=81ukasz_Majewski?= X-Patchwork-Id: 116435 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 99757B6F6F for ; Tue, 27 Sep 2011 01:11:30 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 76538282F4; Mon, 26 Sep 2011 17:11:27 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hoyavHTLgNi6; Mon, 26 Sep 2011 17:11:27 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 70B69282C5; Mon, 26 Sep 2011 17:11:25 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 30CA22827C for ; Mon, 26 Sep 2011 17:10:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7iErO7FjA6y0 for ; Mon, 26 Sep 2011 17:10:40 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) by theia.denx.de (Postfix) with ESMTP id 26AA428253 for ; Mon, 26 Sep 2011 17:10:37 +0200 (CEST) Received: from euspt2 (mailout2.w1.samsung.com [210.118.77.12]) by mailout2.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTP id <0LS4008FSY5ISV@mailout2.w1.samsung.com> for u-boot@lists.denx.de; Mon, 26 Sep 2011 16:10:31 +0100 (BST) Received: from linux.samsung.com ([106.116.38.10]) by spt2.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0LS4008Y9Y5I1I@spt2.w1.samsung.com> for u-boot@lists.denx.de; Mon, 26 Sep 2011 16:10:30 +0100 (BST) Received: from mcdsrvbld02.digital.local (unknown [106.116.37.23]) by linux.samsung.com (Postfix) with ESMTP id 3FF3127004E; Mon, 26 Sep 2011 17:12:35 +0200 (CEST) Date: Mon, 26 Sep 2011 17:10:25 +0200 From: Lukasz Majewski In-reply-to: <1317049825-25751-1-git-send-email-l.majewski@samsung.com> To: u-boot@lists.denx.de Message-id: <1317049825-25751-4-git-send-email-l.majewski@samsung.com> MIME-version: 1.0 X-Mailer: git-send-email 1.7.5.4 References: <1314868412-2949-1-git-send-email-l.majewski@samsung.com> <1317049825-25751-1-git-send-email-l.majewski@samsung.com> Cc: Kyungmin Park , m.szyprowski@samsung.com Subject: [U-Boot] [PATCH 3/3] misc:pmic:mx: Code modification for mx51evk board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This is an example code for adjusting the mx51evk example board to new pmic_core driver. Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park Cc: Stefano Babic --- board/freescale/mx51evk/mx51evk.c | 68 +++++++++++++++++++++++++------------ 1 files changed, 46 insertions(+), 22 deletions(-) diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 94ea1f2..46562f0 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -34,6 +34,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -181,72 +182,94 @@ static void setup_iomux_spi(void) static void power_init(void) { unsigned int val; + struct pmic *p = get_pmic(); struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; /* Write needed to Power Gate 2 register */ - val = pmic_reg_read(REG_POWER_MISC); + if (pmic_reg_read(p, REG_POWER_MISC, &val)) + puts("PMIC write error!\n"); val &= ~PWGT2SPIEN; - pmic_reg_write(REG_POWER_MISC, val); + if (pmic_reg_write(p, REG_POWER_MISC, &val)) + puts("PMIC write error!\n"); /* Externally powered */ - val = pmic_reg_read(REG_CHARGE); + if (pmic_reg_read(p, REG_CHARGE, &val)) + puts("PMIC write error!\n"); val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; - pmic_reg_write(REG_CHARGE, val); + if (pmic_reg_write(p, REG_CHARGE, &val)) + puts("PMIC write error!\n"); /* power up the system first */ - pmic_reg_write(REG_POWER_MISC, PWUP); + val = PWUP; + if (pmic_reg_write(p, REG_POWER_MISC, &val)) + puts("PMIC write error!\n"); /* Set core voltage to 1.1V */ - val = pmic_reg_read(REG_SW_0); + if (pmic_reg_read(p, REG_SW_0, &val)) + puts("PMIC write error!\n"); val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; - pmic_reg_write(REG_SW_0, val); + if (pmic_reg_write(p, REG_SW_0, &val)) + puts("PMIC write error!\n"); /* Setup VCC (SW2) to 1.25 */ - val = pmic_reg_read(REG_SW_1); + if (pmic_reg_read(p, REG_SW_1, &val)) + puts("PMIC write error!\n"); val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; - pmic_reg_write(REG_SW_1, val); + if (pmic_reg_write(p, REG_SW_1, &val)) + puts("PMIC write error!\n"); /* Setup 1V2_DIG1 (SW3) to 1.25 */ - val = pmic_reg_read(REG_SW_2); + if (pmic_reg_read(p, REG_SW_2, &val)) + puts("PMIC write error!\n"); val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; - pmic_reg_write(REG_SW_2, val); - udelay(50); + if (pmic_reg_write(p, REG_SW_2, &val)) + puts("PMIC write error!\n"); /* Raise the core frequency to 800MHz */ writel(0x0, &mxc_ccm->cacrr); /* Set switchers in Auto in NORMAL mode & STANDBY mode */ /* Setup the switcher mode for SW1 & SW2*/ - val = pmic_reg_read(REG_SW_4); + if (pmic_reg_read(p, REG_SW_4, &val)) + puts("PMIC write error!\n"); val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | (SWMODE_MASK << SWMODE2_SHIFT))); val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); - pmic_reg_write(REG_SW_4, val); + if (pmic_reg_write(p, REG_SW_4, &val)) + puts("PMIC write error!\n"); /* Setup the switcher mode for SW3 & SW4 */ - val = pmic_reg_read(REG_SW_5); + if (pmic_reg_read(p, REG_SW_5, &val)) + puts("PMIC write error!\n"); val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | (SWMODE_MASK << SWMODE4_SHIFT))); val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); - pmic_reg_write(REG_SW_5, val); + if (pmic_reg_write(p, REG_SW_5, &val)) + puts("PMIC write error!\n"); /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ - val = pmic_reg_read(REG_SETTING_0); + if (pmic_reg_read(p, REG_SETTING_0, &val)) + puts("PMIC write error!\n"); val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; - pmic_reg_write(REG_SETTING_0, val); + if (pmic_reg_write(p, REG_SETTING_0, &val)) + puts("PMIC write error!\n"); /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ - val = pmic_reg_read(REG_SETTING_1); + if (pmic_reg_read(p, REG_SETTING_1, &val)) + puts("PMIC write error!\n"); val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; - pmic_reg_write(REG_SETTING_1, val); + if (pmic_reg_write(p, REG_SETTING_1, &val)) + puts("PMIC write error!\n"); /* Configure VGEN3 and VCAM regulators to use external PNP */ val = VGEN3CONFIG | VCAMCONFIG; - pmic_reg_write(REG_MODE_1, val); + if (pmic_reg_write(p, REG_MODE_1, &val)) + puts("PMIC write error!\n"); + udelay(200); gpio_direction_output(46, 0); @@ -257,7 +280,8 @@ static void power_init(void) /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | VVIDEOEN | VAUDIOEN | VSDEN; - pmic_reg_write(REG_MODE_1, val); + if (pmic_reg_write(p, REG_MODE_1, &val)) + puts("PMIC write error!\n"); udelay(500);