From patchwork Thu Sep 19 01:20:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 1164254 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-509245-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Hhw/tMx4"; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="cHGym+yE"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46YfDV3k6Sz9s4Y for ; Thu, 19 Sep 2019 11:20:39 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=e6THbFi7kg/R 8j3ag+RpfhYMexQVq3rZg94XJJ/xsZW9r58P9x60A7eC0eplB0FO3xjVjcTJKqmf 0annBIgagsYjE3eEtmxESDi9Z7nsd8rr3P3qB3pMor1SKllaKtjvpQEXkndCqwUx VNoCTJjxKRDX9P+ol164VQXEppj5V4U= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=rGIryS2iC2MBqo3cvP /GlpmleH8=; b=Hhw/tMx4qjjhFosr0/yKjY0RfjoXxF+lsau5mD7q6albZXoFgs FWYIvmAGPR35K5hCqKsuVCdp16HzWX6KTnBYwm/wCv/fN6MTUyiVi0aqigod4pz9 GQ+L3AcZP6XO1rv8rgVqW+JOWvWPvWxuHoWxQS0s9ShK3WIZODJ4SS338= Received: (qmail 106805 invoked by alias); 19 Sep 2019 01:20:32 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 106797 invoked by uid 89); 19 Sep 2019 01:20:31 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-22.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_STOCKGEN, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 spammy=legitimate, H*RU:209.85.210.194, HX-Spam-Relays-External:209.85.210.194 X-HELO: mail-pf1-f194.google.com Received: from mail-pf1-f194.google.com (HELO mail-pf1-f194.google.com) (209.85.210.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 19 Sep 2019 01:20:29 +0000 Received: by mail-pf1-f194.google.com with SMTP id y72so1101304pfb.12 for ; Wed, 18 Sep 2019 18:20:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=gvNqtYu3UP45jlVAW8WZADmebQHTTntOf8o6Re/p9uA=; b=cHGym+yEc35x6ke30pDiOu5WnBzUAGSM9VtCgDY0csOlwAb+NqZnKDf/AOyHwE9dVx y64XQ2UYvV3a6iDTo2rP78i8HSul8Lm8BPUeJygzW5xlaF/1mJupWeHS9Q5PqoumngBz MuTAt+oen6tn+Kt23ZDt17Ly67iBzCdhfI5HXUN27jPkFf9Plom9hSdjIVwQKeVuZFqy BRZ8exRiTIYKAli275ISxPa6AtUhVk/ZUNVTnIh8opFzH5bmMLnwr66e9nNFv2i/bt4O +QcV8KjZgjH3PSL0hDe2kgbzKO46dJhFObFXNLiSeushKH/GstBni/X+p5OKkKE2Y3ot OrNQ== Received: from rohan.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id z20sm4522874pjn.12.2019.09.18.18.20.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2019 18:20:27 -0700 (PDT) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: Jim Wilson Subject: [PATCH] RISC-V: Fix more splitters accidentally calling gen_reg_rtx. Date: Wed, 18 Sep 2019 18:20:24 -0700 Message-Id: <20190919012024.31047-1-jimw@sifive.com> X-IsSubscribed: yes Similar to a previous patch, adding a in_splitter arg to every function that can be called from a define_split, so we can prevent calls to gen_reg_rtx during combine, which can cause crashes. Tested with riscv32-elf and riscv64-linux builds and checks with no regressions. Commmitted. Jim PR target/91683 * config/riscv/riscv-protos.h (riscv_split_symbol): New bool parameter. (riscv_move_integer): Likewise. * config/riscv/riscv.c (riscv_split_integer): Pass FALSE for new riscv_move_integer arg. (riscv_legitimize_move): Likewise. (riscv_force_temporary): New parameter in_splitter. Don't call force_reg if true. (riscv_unspec_offset_high): Pass FALSE for new riscv_force_temporary arg. (riscv_add_offset): Likewise. (riscv_split_symbol): New parameter in_splitter. Pass to riscv_force_temporary. (riscv_legitimize_address): Pass FALSE for new riscv_split_symbol arg. (riscv_move_integer): New parameter in_splitter. New local can_create_psuedo. Don't call riscv_split_integer or force_reg when in_splitter TRUE. (riscv_legitimize_const_move): Pass FALSE for new riscv_move_integer, riscv_split_symbol, and riscv_force_temporary args. * config/riscv/riscv.md (low+1): Pass TRUE for new riscv_move_integer arg. (low+2): Pass TRUE for new riscv_split_symbol arg. --- gcc/config/riscv/riscv-protos.h | 4 +-- gcc/config/riscv/riscv.c | 46 ++++++++++++++++++++------------- gcc/config/riscv/riscv.md | 6 ++--- 3 files changed, 33 insertions(+), 23 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 69e39f7a208..5092294803c 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -44,10 +44,10 @@ extern int riscv_const_insns (rtx); extern int riscv_split_const_insns (rtx); extern int riscv_load_store_insns (rtx, rtx_insn *); extern rtx riscv_emit_move (rtx, rtx); -extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *); +extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *, bool); extern bool riscv_split_symbol_type (enum riscv_symbol_type); extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type); -extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode); +extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode, bool); extern bool riscv_legitimize_move (machine_mode, rtx, rtx); extern rtx riscv_subword (rtx, bool); extern bool riscv_split_64bit_move_p (rtx, rtx); diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 39bf87abf1c..b8a8778b92c 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -508,8 +508,8 @@ riscv_split_integer (HOST_WIDE_INT val, machine_mode mode) unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode); - riscv_move_integer (hi, hi, hival, mode); - riscv_move_integer (lo, lo, loval, mode); + riscv_move_integer (hi, hi, hival, mode, FALSE); + riscv_move_integer (lo, lo, loval, mode, FALSE); hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32)); hi = force_reg (mode, hi); @@ -1021,9 +1021,12 @@ riscv_force_binary (machine_mode mode, enum rtx_code code, rtx x, rtx y) are allowed, copy it into a new register, otherwise use DEST. */ static rtx -riscv_force_temporary (rtx dest, rtx value) +riscv_force_temporary (rtx dest, rtx value, bool in_splitter) { - if (can_create_pseudo_p ()) + /* We can't call gen_reg_rtx from a splitter, because this might realloc + the regno_reg_rtx array, which would invalidate reg rtx pointers in the + combine undo buffer. */ + if (can_create_pseudo_p () && !in_splitter) return force_reg (Pmode, value); else { @@ -1082,7 +1085,7 @@ static rtx riscv_unspec_offset_high (rtx temp, rtx addr, enum riscv_symbol_type symbol_type) { addr = gen_rtx_HIGH (Pmode, riscv_unspec_address (addr, symbol_type)); - return riscv_force_temporary (temp, addr); + return riscv_force_temporary (temp, addr, FALSE); } /* Load an entry from the GOT for a TLS GD access. */ @@ -1130,7 +1133,8 @@ static rtx riscv_tls_add_tp_le (rtx dest, rtx base, rtx sym) is guaranteed to be a legitimate address for mode MODE. */ bool -riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out) +riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out, + bool in_splitter) { enum riscv_symbol_type symbol_type; @@ -1146,7 +1150,7 @@ riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out) case SYMBOL_ABSOLUTE: { rtx high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); - high = riscv_force_temporary (temp, high); + high = riscv_force_temporary (temp, high, in_splitter); *low_out = gen_rtx_LO_SUM (Pmode, high, addr); } break; @@ -1205,8 +1209,9 @@ riscv_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) overflow, so we need to force a sign-extension check. */ high = gen_int_mode (CONST_HIGH_PART (offset), Pmode); offset = CONST_LOW_PART (offset); - high = riscv_force_temporary (temp, high); - reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg)); + high = riscv_force_temporary (temp, high, FALSE); + reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg), + FALSE); } return plus_constant (Pmode, reg, offset); } @@ -1315,7 +1320,7 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, return riscv_legitimize_tls_address (x); /* See if the address can split into a high part and a LO_SUM. */ - if (riscv_split_symbol (NULL, x, mode, &addr)) + if (riscv_split_symbol (NULL, x, mode, &addr, FALSE)) return riscv_force_address (addr, mode); /* Handle BASE + OFFSET using riscv_add_offset. */ @@ -1339,19 +1344,24 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, void riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, - machine_mode orig_mode) + machine_mode orig_mode, bool in_splitter) { struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; machine_mode mode; int i, num_ops; rtx x; + /* We can't call gen_reg_rtx from a splitter, because this might realloc + the regno_reg_rtx array, which would invalidate reg rtx pointers in the + combine undo buffer. */ + bool can_create_pseudo = can_create_pseudo_p () && ! in_splitter; + mode = GET_MODE (dest); /* We use the original mode for the riscv_build_integer call, because HImode values are given special treatment. */ num_ops = riscv_build_integer (codes, value, orig_mode); - if (can_create_pseudo_p () && num_ops > 2 /* not a simple constant */ + if (can_create_pseudo && num_ops > 2 /* not a simple constant */ && num_ops >= riscv_split_integer_cost (value)) x = riscv_split_integer (value, mode); else @@ -1361,7 +1371,7 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, for (i = 1; i < num_ops; i++) { - if (!can_create_pseudo_p ()) + if (!can_create_pseudo) x = riscv_emit_set (temp, x); else x = force_reg (mode, x); @@ -1385,12 +1395,12 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) /* Split moves of big integers into smaller pieces. */ if (splittable_const_int_operand (src, mode)) { - riscv_move_integer (dest, dest, INTVAL (src), mode); + riscv_move_integer (dest, dest, INTVAL (src), mode, FALSE); return; } /* Split moves of symbolic constants into high/low pairs. */ - if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src)) + if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src, FALSE)) { riscv_emit_set (dest, src); return; @@ -1411,7 +1421,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) if (offset != const0_rtx && (targetm.cannot_force_const_mem (mode, src) || can_create_pseudo_p ())) { - base = riscv_force_temporary (dest, base); + base = riscv_force_temporary (dest, base, FALSE); riscv_emit_move (dest, riscv_add_offset (NULL, base, INTVAL (offset))); return; } @@ -1420,7 +1430,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) /* When using explicit relocs, constant pool references are sometimes not legitimate addresses. */ - riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0)); + riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0), FALSE); riscv_emit_move (dest, src); } @@ -1446,7 +1456,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) if (splittable_const_int_operand (src, mode)) { reg = gen_reg_rtx (promoted_mode); - riscv_move_integer (reg, reg, INTVAL (src), mode); + riscv_move_integer (reg, reg, INTVAL (src), mode, FALSE); } else reg = force_reg (promoted_mode, src); diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 744a027a1b7..d3c8f659748 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1285,7 +1285,7 @@ [(const_int 0)] { riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]), - mode); + mode, TRUE); DONE; }) @@ -1294,11 +1294,11 @@ [(set (match_operand:P 0 "register_operand") (match_operand:P 1)) (clobber (match_operand:P 2 "register_operand"))] - "riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)" + "riscv_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL, TRUE)" [(set (match_dup 0) (match_dup 3))] { riscv_split_symbol (operands[2], operands[1], - MAX_MACHINE_MODE, &operands[3]); + MAX_MACHINE_MODE, &operands[3], TRUE); }) ;; 64-bit integer moves