[v2] pwm: stm32-lp: add check in case requested period cannot be achieved
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Message ID 1568818461-19995-1-git-send-email-fabrice.gasnier@st.com
State Accepted
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Series
  • [v2] pwm: stm32-lp: add check in case requested period cannot be achieved
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Commit Message

Fabrice Gasnier Sept. 18, 2019, 2:54 p.m. UTC
LPTimer can use a 32KHz clock for counting. It depends on clock tree
configuration. In such a case, PWM output frequency range is limited.
Although unlikely, nothing prevents user from requesting a PWM frequency
above counting clock (32KHz for instance):
- This causes (prd - 1) = 0xffff to be written in ARR register later in
the apply() routine.
This results in badly configured PWM period (and also duty_cycle).
Add a check to report an error is such a case.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
---
Changes in v2:
- remarks from Uwe: update the comment, use dev_dbg() and print period that
  cannot be reached
---
 drivers/pwm/pwm-stm32-lp.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Uwe Kleine-König Sept. 18, 2019, 6:40 p.m. UTC | #1
On Wed, Sep 18, 2019 at 04:54:21PM +0200, Fabrice Gasnier wrote:
> LPTimer can use a 32KHz clock for counting. It depends on clock tree
> configuration. In such a case, PWM output frequency range is limited.
> Although unlikely, nothing prevents user from requesting a PWM frequency
> above counting clock (32KHz for instance):
> - This causes (prd - 1) = 0xffff to be written in ARR register later in
> the apply() routine.
> This results in badly configured PWM period (and also duty_cycle).
> Add a check to report an error is such a case.
> 
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

If you are interested to improve the driver further, there are a few
things that I would welcome to see fixed in a tested patch:

 - duty calculation uses requested instead of implemented period.
 - stm32_pwm_lp_apply calls pwm_get_state
 - Calculation of prd could be done without a loop
 - A hint about relevant documentation in the driver's header would be
   great
 - Documentation about behaviour of the hardware is missing:
   - Does the hardware complete the currently running period when
     STM32_LPTIM_CR is cleared?
   - Does the output stop in the inactive output level when the PWM is
     stopped?
 - clk_get_rate might be called without the clock being enabled.
 - The driver does:

 	ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty));

   That looks wrong. (Consider dty == prd.)

Best regards
Uwe

Patch
diff mbox series

diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c
index 2211a64..97a9afa 100644
--- a/drivers/pwm/pwm-stm32-lp.c
+++ b/drivers/pwm/pwm-stm32-lp.c
@@ -59,6 +59,12 @@  static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	/* Calculate the period and prescaler value */
 	div = (unsigned long long)clk_get_rate(priv->clk) * state->period;
 	do_div(div, NSEC_PER_SEC);
+	if (!div) {
+		/* Clock is too slow to achieve requested period. */
+		dev_dbg(priv->chip.dev, "Can't reach %u ns\n",	state->period);
+		return -EINVAL;
+	}
+
 	prd = div;
 	while (div > STM32_LPTIM_MAX_ARR) {
 		presc++;