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Miller" , Greg Kroah-Hartman , Linus Walleij , Nicolas Ferre , "Paul E. McKenney" , , , Subject: [v7 2/2] dt-bindings: mtd: Add Cadence NAND controller driver Date: Wed, 18 Sep 2019 13:31:45 +0100 Message-ID: <20190918123223.31745-1-piotrs@cadence.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20190918122923.28737-1-piotrs@cadence.com> References: <20190918122923.28737-1-piotrs@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:158.140.1.28; IPV:CAL; SCL:-1; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(39860400002)(136003)(396003)(346002)(376002)(199004)(189003)(36092001)(478600001)(87636003)(5660300002)(70586007)(70206006)(109986005)(2906002)(76130400001)(42186006)(50226002)(4326008)(16586007)(48376002)(54906003)(316002)(486006)(7636002)(305945005)(1076003)(8936002)(1671002)(356004)(7416002)(50466002)(2616005)(336012)(36756003)(26826003)(6666004)(446003)(76176011)(426003)(86362001)(186003)(51416003)(26005)(476003)(47776003)(126002)(8676002)(246002)(11346002)(266003); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR07MB3865; H:sjmaillnx2.cadence.com; FPR:; SPF:SoftFail; LANG:en; PTR:corp.Cadence.COM; A:1; MX:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a20fe372-a398-416c-5a57-08d73c346cfe X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600167)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328); SRVR:DM5PR07MB3865; X-MS-TrafficTypeDiagnostic: DM5PR07MB3865: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:525; X-Forefront-PRVS: 01644DCF4A X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: 3R6BftLp8SE2ipIBNr0pNyn/ZMkwS8RAsm4U4+nc0JEA02Puyo7xVqjdu8Pe2S8DHpklX1wp2at2P71BgsXruUAVSA22pyBz0gYBdxsUq7bucAZDK8ZKesOOp6UBmpx2otey5lJqPGg6daqmxW60ZMcxevtTCHH9oEBTFcqd9QqSol8wJnYK3fprbmw/Auy5GRaTPDtdGxOVaORPTb24X0tNG/5PymvbTK08/8V/MDOZhT1NRFvOUglVk/NvqUkodjGRPCrZFncIr2zlOKuaackZGEEeV4MoAM4FXtklexXy478+8K2IAWR32TmxAJ1o7vCyH+eZ4FhFm4tbP5ekUW4jUUBbmlBxYDctnnqe1r/hcmuvFi1q+j7URD7DVwkKG8EsFZnexwMNVnLIkO7ZuHtKrXi/Vvyy4u5qJZC95tE= X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2019 12:33:36.0328 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a20fe372-a398-416c-5a57-08d73c346cfe X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9; Ip=[158.140.1.28]; Helo=[sjmaillnx2.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR07MB3865 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-09-18_07:2019-09-17,2019-09-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 malwarescore=0 suspectscore=0 adultscore=0 phishscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1909180128 To: unlisted-recipients:; (no To-header on input) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the bindings used by Cadence NAND controller driver Signed-off-by: Piotr Sroka Reviewed-by: Rob Herring --- Changes for v7: - none Changes for v6: - add documentation for address-cells and size-cells - remove not needed space - put myself as maintainer of the Cadence nand driver bindings Changes for v5: - replace "_" by "-" in all properties - change compatible name from cdns,hpnfc to cdns,hp-nfc Changes for v4: - add commit message Changes for v3: - add unit suffix for board_delay - move child description to proper place - remove prefix cadence_ for reg and sdma fields Changes for v2: - remove chip dependends parameters from dts bindings - add names for register ranges in dts bindings - add generic bindings to describe NAND chip representation --- .../bindings/mtd/cadence-nand-controller.txt | 53 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt diff --git a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt new file mode 100644 index 000000000000..f3893c4d3c6a --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt @@ -0,0 +1,53 @@ +* Cadence NAND controller + +Required properties: + - compatible : "cdns,hp-nfc" + - reg : Contains two entries, each of which is a tuple consisting of a + physical address and length. The first entry is the address and + length of the controller register set. The second entry is the + address and length of the Slave DMA data port. + - reg-names: should contain "reg" and "sdma" + - #address-cells: should be 1. The cell encodes the chip select connection. + - #size-cells : should be 0. + - interrupts : The interrupt number. + - clocks: phandle of the controller core clock (nf_clk). + +Optional properties: + - dmas: shall reference DMA channel associated to the NAND controller + - cdns,board-delay-ps : Estimated Board delay. The value includes the total + round trip delay for the signals and is used for deciding on values + associated with data read capture. The example formula for SDR mode is + the following: + board delay = RE#PAD delay + PCB trace to device + PCB trace from device + + DQ PAD delay + +Child nodes represent the available NAND chips. + +Required properties of NAND chips: + - reg: shall contain the native Chip Select ids from 0 to max supported by + the cadence nand flash controller + +See Documentation/devicetree/bindings/mtd/nand.txt for more details on +generic bindings. + +Example: + +nand_controller: nand-controller@60000000 { + compatible = "cdns,hp-nfc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x60000000 0x10000>, <0x80000000 0x10000>; + reg-names = "reg", "sdma"; + clocks = <&nf_clk>; + cdns,board-delay-ps = <4830>; + interrupts = <2 0>; + nand@0 { + reg = <0>; + label = "nand-1"; + }; + nand@1 { + reg = <1>; + label = "nand-2"; + }; + +}; diff --git a/MAINTAINERS b/MAINTAINERS index 16e16445b88b..94d78f4e29ba 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3584,6 +3584,7 @@ M: Piotr Sroka L: linux-mtd@lists.infradead.org S: Maintained F: drivers/mtd/nand/raw/cadence-nand-controller.c +F: Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt CADET FM/AM RADIO RECEIVER DRIVER M: Hans Verkuil