diff mbox series

[U-Boot,v2] armv7: ls102xa: Correct entry of SCFG_QSPI_CLKSEL

Message ID 1568804284-25162-1-git-send-email-kuldeep.singh@nxp.com
State Accepted
Commit bb6f3c0f76347a3a8d701f2318bbf0b7eef5279e
Delegated to: Priyanka Jain
Headers show
Series [U-Boot,v2] armv7: ls102xa: Correct entry of SCFG_QSPI_CLKSEL | expand

Commit Message

Kuldeep Singh Sept. 18, 2019, 10:58 a.m. UTC 
Value 0xC is reserved. Replace it with correct value 0x5 which
is ClusterPLL/16

Signed-off-by: Ashish Kumar <Ashish.kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
---
v2:
Reword commit message
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Priyanka Jain Oct. 22, 2019, 4:36 a.m. UTC | #1 
>-----Original Message-----
>From: Kuldeep Singh <kuldeep.singh@nxp.com>
>Sent: Wednesday, September 18, 2019 4:28 PM
>To: u-boot@lists.denx.de
>Cc: albert.u.boot@aribaud.net; Priyanka Jain <priyanka.jain@nxp.com>; Ran
>Wang <ran.wang_1@nxp.com>; Peng Ma <peng.ma@nxp.com>; Kuldeep Singh
><kuldeep.singh@nxp.com>; Ashish Kumar <ashish.kumar@nxp.com>
>Subject: [PATCH v2] armv7: ls102xa: Correct entry of SCFG_QSPI_CLKSEL
>
>Value 0xC is reserved. Replace it with correct value 0x5 which is ClusterPLL/16
>
>Signed-off-by: Ashish Kumar <Ashish.kumar@nxp.com>
>Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
>---
<snip>

Slight update in subject and description.
Applied to fsl-qoriq master, awaiting upstream.

Thanks
priyankajain
diff mbox series

Patch

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 137cd61804..f2ba182346 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -155,7 +155,7 @@  struct ccsr_gur {
 #define SCFG_ETSECCMCR_GE0_CLK125	0x00000000
 #define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
 #define SCFG_PIXCLKCR_PXCKEN		0x80000000
-#define SCFG_QSPI_CLKSEL		0xc0100000
+#define SCFG_QSPI_CLKSEL		0x50100000
 #define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
 #define SCFG_SNPCNFGCR_DCU_RD_WR	0x03000000
 #define SCFG_SNPCNFGCR_SATA_RD_WR	0x00c00000