[v3,1/2] clk: ti: am3: Update AM3 GPIO number as per datasheet
diff mbox series

Message ID 20190917234829.91132-2-ankur.tyagi@gallagher.com
State Changes Requested
Headers show
Series
  • Update AM3/4 GPIO number as per datasheet
Related show

Checks

Context Check Description
robh/checkpatch warning "total: 0 errors, 5 warnings, 204 lines checked"

Commit Message

Ankur Tyagi Sept. 17, 2019, 11:48 p.m. UTC
Sitara technical reference manual numbers GPIO from 0 whereas in
code GPIO are numbered from 1

Signed-off-by: Ankur Tyagi <ankur.tyagi@gallagher.com>
---
 arch/arm/boot/dts/am33xx-l4.dtsi | 24 ++++++++++++------------
 drivers/clk/ti/clk-33xx-compat.c | 12 ++++++------
 drivers/clk/ti/clk-33xx.c        | 12 ++++++------
 include/dt-bindings/clock/am3.h  | 16 ++++++++--------
 4 files changed, 32 insertions(+), 32 deletions(-)

Comments

Tony Lindgren Sept. 18, 2019, 3:20 p.m. UTC | #1
Hi,

* Ankur Tyagi <ankur.tyagi@gallagher.com> [190917 23:49]:
> Sitara technical reference manual numbers GPIO from 0 whereas in
> code GPIO are numbered from 1

If this is a cosmetic fix, please add it to the description.
Then if there is also some other fix, that should be done
separately

> --- a/arch/arm/boot/dts/am33xx-l4.dtsi
> +++ b/arch/arm/boot/dts/am33xx-l4.dtsi
> @@ -129,7 +129,7 @@
>  
>  		target-module@7000 {			/* 0x44e07000, ap 14 20.0 */
>  			compatible = "ti,sysc-omap2", "ti,sysc";
> -			ti,hwmods = "gpio1";
> +			ti,hwmods = "gpio0";
>  			reg = <0x7000 0x4>,
>  			      <0x7010 0x4>,
>  			      <0x7114 0x4>;

Let's simplify things a bit first :) We should be able to drop
the "ti,hwmods" property for all gpio instances and the related
platform data. I'll post a patch for that after -rc1.

If there's some non-cosmetic fix here too, we should naturally
apply a fix for that first.


> -			clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
> -				 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>;
> +			clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO0_CLKCTRL 0>,
> +				 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO0_CLKCTRL 18>;

Not sure if this renumbering helps.. It might actually make it easier
to introduce weird bugs if older dtb is used with a newer kernel.

> @@ -72,9 +72,9 @@ static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst
>  	{ AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
>  	{ AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
>  	{ AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
> +	{ AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
>  	{ AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
>  	{ AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
> -	{ AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
>  	{ AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
>  	{ AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
>  	{ AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },

So is this just renumbering, or do we have some other real bug
too here?

Regards,

Tony
Ankur Tyagi Sept. 18, 2019, 9:43 p.m. UTC | #2
Hi,

> -----Original Message-----
> From: Tony Lindgren <tony@atomide.com>
> Sent: Thursday, 19 September 2019 3:21 AM
> To: Ankur Tyagi <Ankur.Tyagi@gallagher.com>
> Cc: t-kristo@ti.com; mturquette@baylibre.com; sboyd@kernel.org; linux-
> omap@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v3 1/2] clk: ti: am3: Update AM3 GPIO number as per
> datasheet
>
> Hi,
>
> * Ankur Tyagi <ankur.tyagi@gallagher.com> [190917 23:49]:
> > Sitara technical reference manual numbers GPIO from 0 whereas in code
> > GPIO are numbered from 1
>
> If this is a cosmetic fix, please add it to the description.
> Then if there is also some other fix, that should be done separately

This is a cosmetic fix only. Shall I send v4 with new description?

> > --- a/arch/arm/boot/dts/am33xx-l4.dtsi
> > +++ b/arch/arm/boot/dts/am33xx-l4.dtsi
> > @@ -129,7 +129,7 @@
> >
> >  target-module@7000 {/* 0x44e07000, ap 14
> 20.0 */
> >  compatible = "ti,sysc-omap2", "ti,sysc";
> > -ti,hwmods = "gpio1";
> > +ti,hwmods = "gpio0";
> >  reg = <0x7000 0x4>,
> >        <0x7010 0x4>,
> >        <0x7114 0x4>;
>
> Let's simplify things a bit first :) We should be able to drop the "ti,hwmods"
> property for all gpio instances and the related platform data. I'll post a patch
> for that after -rc1.
>
> If there's some non-cosmetic fix here too, we should naturally apply a fix for
> that first.

No, there is no other fix here

>
> > -clocks = <&l4_wkup_clkctrl
> AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
> > - <&l4_wkup_clkctrl
> AM3_L4_WKUP_GPIO1_CLKCTRL 18>;
> > +clocks = <&l4_wkup_clkctrl
> AM3_L4_WKUP_GPIO0_CLKCTRL 0>,
> > + <&l4_wkup_clkctrl
> AM3_L4_WKUP_GPIO0_CLKCTRL 18>;
>
> Not sure if this renumbering helps.. It might actually make it easier to
> introduce weird bugs if older dtb is used with a newer kernel.

Actually I had some trouble with old version of kernel where I just used
GPIO2 define to enable gpio2 clock but it enabled gpio1. That's why I thought
of fixing the numbering in code.

> > @@ -72,9 +72,9 @@ static const struct omap_clkctrl_reg_data
> am3_l4_per_clkctrl_regs[] __initconst
> >  { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
> >  { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
> >  { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm"
> },
> > +{ AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP,
> "l4ls_gclk" },
> >  { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP,
> "l4ls_gclk" },
> >  { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP,
> "l4ls_gclk" },
> > -{ AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP,
> "l4ls_gclk" },
> >  { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
> >  { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
> >  { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
>
> So is this just renumbering, or do we have some other real bug too here?

Just numbering to make things consistent with reference manual.
Let me know if it is worth doing then I'll send another patch with updated
description otherwise not 😊

> Regards,
>
> Tony

Regards
Ankur
Tony Lindgren Sept. 18, 2019, 9:48 p.m. UTC | #3
* Ankur Tyagi <Ankur.Tyagi@gallagher.com> [190918 21:44]:
> Hi,
> 
> > -----Original Message-----
> > From: Tony Lindgren <tony@atomide.com>
> > Sent: Thursday, 19 September 2019 3:21 AM
> > To: Ankur Tyagi <Ankur.Tyagi@gallagher.com>
> > Cc: t-kristo@ti.com; mturquette@baylibre.com; sboyd@kernel.org; linux-
> > omap@vger.kernel.org; devicetree@vger.kernel.org
> > Subject: Re: [PATCH v3 1/2] clk: ti: am3: Update AM3 GPIO number as per
> > datasheet
> >
> > Hi,
> >
> > * Ankur Tyagi <ankur.tyagi@gallagher.com> [190917 23:49]:
> > > Sitara technical reference manual numbers GPIO from 0 whereas in code
> > > GPIO are numbered from 1
> >
> > If this is a cosmetic fix, please add it to the description.
> > Then if there is also some other fix, that should be done separately
> 
> This is a cosmetic fix only. Shall I send v4 with new description?

Well if this is a cosmetic fix only, let's wait a bit so we can get
rid of the "ti,hwmods" part. I'll post patches for that after -rc,
so in few weeks. But yeah when reposting at that point, just add
"no functional changes" to the patch to make it clear.

> > > --- a/arch/arm/boot/dts/am33xx-l4.dtsi
> > > +++ b/arch/arm/boot/dts/am33xx-l4.dtsi
> > > @@ -129,7 +129,7 @@
> > >
> > >  target-module@7000 {/* 0x44e07000, ap 14
> > 20.0 */
> > >  compatible = "ti,sysc-omap2", "ti,sysc";
> > > -ti,hwmods = "gpio1";
> > > +ti,hwmods = "gpio0";
> > >  reg = <0x7000 0x4>,
> > >        <0x7010 0x4>,
> > >        <0x7114 0x4>;
> >
> > Let's simplify things a bit first :) We should be able to drop the "ti,hwmods"
> > property for all gpio instances and the related platform data. I'll post a patch
> > for that after -rc1.
> >
> > If there's some non-cosmetic fix here too, we should naturally apply a fix for
> > that first.
> 
> No, there is no other fix here

OK thanks for confirming it.

> > > -clocks = <&l4_wkup_clkctrl
> > AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
> > > - <&l4_wkup_clkctrl
> > AM3_L4_WKUP_GPIO1_CLKCTRL 18>;
> > > +clocks = <&l4_wkup_clkctrl
> > AM3_L4_WKUP_GPIO0_CLKCTRL 0>,
> > > + <&l4_wkup_clkctrl
> > AM3_L4_WKUP_GPIO0_CLKCTRL 18>;
> >
> > Not sure if this renumbering helps.. It might actually make it easier to
> > introduce weird bugs if older dtb is used with a newer kernel.
> 
> Actually I had some trouble with old version of kernel where I just used
> GPIO2 define to enable gpio2 clock but it enabled gpio1. That's why I thought
> of fixing the numbering in code.

Yeah fixing it makes things easier to follow :)

> > > @@ -72,9 +72,9 @@ static const struct omap_clkctrl_reg_data
> > am3_l4_per_clkctrl_regs[] __initconst
> > >  { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
> > >  { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
> > >  { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm"
> > },
> > > +{ AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP,
> > "l4ls_gclk" },
> > >  { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP,
> > "l4ls_gclk" },
> > >  { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP,
> > "l4ls_gclk" },
> > > -{ AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP,
> > "l4ls_gclk" },
> > >  { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
> > >  { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
> > >  { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
> >
> > So is this just renumbering, or do we have some other real bug too here?
> 
> Just numbering to make things consistent with reference manual.
> Let me know if it is worth doing then I'll send another patch with updated
> description otherwise not 😊

OK yeah let's wait a bit. Tero might have more comments too.

Regards,

Tony
Ankur Tyagi Sept. 18, 2019, 10:01 p.m. UTC | #4
Hi,

> -----Original Message-----
> From: Tony Lindgren <tony@atomide.com>
> Sent: Thursday, 19 September 2019 9:48 AM
> To: Ankur Tyagi <Ankur.Tyagi@gallagher.com>
> Cc: t-kristo@ti.com; mturquette@baylibre.com; sboyd@kernel.org; linux-
> omap@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v3 1/2] clk: ti: am3: Update AM3 GPIO number as per
> datasheet
>
> * Ankur Tyagi <Ankur.Tyagi@gallagher.com> [190918 21:44]:
> > Hi,
> >
> > > -----Original Message-----
> > > From: Tony Lindgren <tony@atomide.com>
> > > Sent: Thursday, 19 September 2019 3:21 AM
> > > To: Ankur Tyagi <Ankur.Tyagi@gallagher.com>
> > > Cc: t-kristo@ti.com; mturquette@baylibre.com; sboyd@kernel.org;
> > > linux- omap@vger.kernel.org; devicetree@vger.kernel.org
> > > Subject: Re: [PATCH v3 1/2] clk: ti: am3: Update AM3 GPIO number as
> > > per datasheet
> > >
> > > Hi,
> > >
> > > * Ankur Tyagi <ankur.tyagi@gallagher.com> [190917 23:49]:
> > > > Sitara technical reference manual numbers GPIO from 0 whereas in
> > > > code GPIO are numbered from 1
> > >
> > > If this is a cosmetic fix, please add it to the description.
> > > Then if there is also some other fix, that should be done separately
> >
> > This is a cosmetic fix only. Shall I send v4 with new description?
>
> Well if this is a cosmetic fix only, let's wait a bit so we can get rid of the
> "ti,hwmods" part. I'll post patches for that after -rc, so in few weeks. But
> yeah when reposting at that point, just add "no functional changes" to the
> patch to make it clear.

Sure, I'll wait

> > > > --- a/arch/arm/boot/dts/am33xx-l4.dtsi
> > > > +++ b/arch/arm/boot/dts/am33xx-l4.dtsi
> > > > @@ -129,7 +129,7 @@
> > > >
> > > >  target-module@7000 {/* 0x44e07000, ap 14
> > > 20.0 */
> > > >  compatible = "ti,sysc-omap2", "ti,sysc"; -ti,hwmods = "gpio1";
> > > > +ti,hwmods = "gpio0";
> > > >  reg = <0x7000 0x4>,
> > > >        <0x7010 0x4>,
> > > >        <0x7114 0x4>;
> > >
> > > Let's simplify things a bit first :) We should be able to drop the
> "ti,hwmods"
> > > property for all gpio instances and the related platform data. I'll
> > > post a patch for that after -rc1.
> > >
> > > If there's some non-cosmetic fix here too, we should naturally apply
> > > a fix for that first.
> >
> > No, there is no other fix here
>
> OK thanks for confirming it.
>
> > > > -clocks = <&l4_wkup_clkctrl
> > > AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
> > > > - <&l4_wkup_clkctrl
> > > AM3_L4_WKUP_GPIO1_CLKCTRL 18>;
> > > > +clocks = <&l4_wkup_clkctrl
> > > AM3_L4_WKUP_GPIO0_CLKCTRL 0>,
> > > > + <&l4_wkup_clkctrl
> > > AM3_L4_WKUP_GPIO0_CLKCTRL 18>;
> > >
> > > Not sure if this renumbering helps.. It might actually make it
> > > easier to introduce weird bugs if older dtb is used with a newer kernel.
> >
> > Actually I had some trouble with old version of kernel where I just
> > used
> > GPIO2 define to enable gpio2 clock but it enabled gpio1. That's why I
> > thought of fixing the numbering in code.
>
> Yeah fixing it makes things easier to follow :)

Thanks 😊

> > > > @@ -72,9 +72,9 @@ static const struct omap_clkctrl_reg_data
> > > am3_l4_per_clkctrl_regs[] __initconst
> > > >  { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },  {
> > > > AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },  {
> > > > AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm"
> > > },
> > > > +{ AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP,
> > > "l4ls_gclk" },
> > > >  { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP,
> > > "l4ls_gclk" },
> > > >  { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP,
> > > "l4ls_gclk" },
> > > > -{ AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP,
> > > "l4ls_gclk" },
> > > >  { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
> > > > { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },  {
> > > > AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
> > >
> > > So is this just renumbering, or do we have some other real bug too here?
> >
> > Just numbering to make things consistent with reference manual.
> > Let me know if it is worth doing then I'll send another patch with
> > updated description otherwise not 😊
>
> OK yeah let's wait a bit. Tero might have more comments too.


Sure, will wait for his comments and your patch


> Regards,
>
> Tony

Regards
Ankur

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
index 46849d6ecb3e..cc0414ccaf29 100644
--- a/arch/arm/boot/dts/am33xx-l4.dtsi
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
@@ -129,7 +129,7 @@ 
 
 		target-module@7000 {			/* 0x44e07000, ap 14 20.0 */
 			compatible = "ti,sysc-omap2", "ti,sysc";
-			ti,hwmods = "gpio1";
+			ti,hwmods = "gpio0";
 			reg = <0x7000 0x4>,
 			      <0x7010 0x4>,
 			      <0x7114 0x4>;
@@ -143,8 +143,8 @@ 
 					<SYSC_IDLE_SMART_WKUP>;
 			ti,syss-mask = <1>;
 			/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
-			clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
-				 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>;
+			clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO0_CLKCTRL 0>,
+				 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO0_CLKCTRL 18>;
 			clock-names = "fck", "dbclk";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -1270,7 +1270,7 @@ 
 
 		target-module@4c000 {			/* 0x4804c000, ap 32 36.0 */
 			compatible = "ti,sysc-omap2", "ti,sysc";
-			ti,hwmods = "gpio2";
+			ti,hwmods = "gpio1";
 			reg = <0x4c000 0x4>,
 			      <0x4c010 0x4>,
 			      <0x4c114 0x4>;
@@ -1284,8 +1284,8 @@ 
 					<SYSC_IDLE_SMART_WKUP>;
 			ti,syss-mask = <1>;
 			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
-			clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>,
-				 <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>;
+			clocks = <&l4ls_clkctrl AM3_L4LS_GPIO1_CLKCTRL 0>,
+				 <&l4ls_clkctrl AM3_L4LS_GPIO1_CLKCTRL 18>;
 			clock-names = "fck", "dbclk";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -1682,7 +1682,7 @@ 
 
 		target-module@ac000 {			/* 0x481ac000, ap 54 38.0 */
 			compatible = "ti,sysc-omap2", "ti,sysc";
-			ti,hwmods = "gpio3";
+			ti,hwmods = "gpio2";
 			reg = <0xac000 0x4>,
 			      <0xac010 0x4>,
 			      <0xac114 0x4>;
@@ -1696,8 +1696,8 @@ 
 					<SYSC_IDLE_SMART_WKUP>;
 			ti,syss-mask = <1>;
 			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
-			clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>,
-				 <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>;
+			clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>,
+				 <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>;
 			clock-names = "fck", "dbclk";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -1716,7 +1716,7 @@ 
 
 		target-module@ae000 {			/* 0x481ae000, ap 56 3a.0 */
 			compatible = "ti,sysc-omap2", "ti,sysc";
-			ti,hwmods = "gpio4";
+			ti,hwmods = "gpio3";
 			reg = <0xae000 0x4>,
 			      <0xae010 0x4>,
 			      <0xae114 0x4>;
@@ -1730,8 +1730,8 @@ 
 					<SYSC_IDLE_SMART_WKUP>;
 			ti,syss-mask = <1>;
 			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
-			clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>,
-				 <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>;
+			clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>,
+				 <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>;
 			clock-names = "fck", "dbclk";
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/drivers/clk/ti/clk-33xx-compat.c b/drivers/clk/ti/clk-33xx-compat.c
index 3e07f127912a..7c80522a577a 100644
--- a/drivers/clk/ti/clk-33xx-compat.c
+++ b/drivers/clk/ti/clk-33xx-compat.c
@@ -28,17 +28,17 @@  static const char * const am3_gpio1_dbclk_parents[] __initconst = {
 	NULL,
 };
 
-static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
+static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
 	{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
 	{ 0 },
 };
 
-static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
+static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
 	{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
 	{ 0 },
 };
 
-static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
+static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
 	{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
 	{ 0 },
 };
@@ -72,9 +72,9 @@  static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst
 	{ AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
 	{ AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
 	{ AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+	{ AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
 	{ AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
 	{ AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
-	{ AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
 	{ AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
 	{ AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
 	{ AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
@@ -103,7 +103,7 @@  static const char * const am3_gpio0_dbclk_parents[] __initconst = {
 	NULL,
 };
 
-static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
+static const struct omap_clkctrl_bit_data am3_gpio0_bit_data[] __initconst = {
 	{ 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
 	{ 0 },
 };
@@ -156,7 +156,7 @@  static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
 
 static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
 	{ AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
-	{ AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
+	{ AM3_GPIO0_CLKCTRL, am3_gpio0_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
 	{ AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
 	{ AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
 	{ AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index a360d3109555..d67f1f6bbec0 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -28,17 +28,17 @@  static const char * const am3_gpio1_dbclk_parents[] __initconst = {
 	NULL,
 };
 
-static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
+static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
 	{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
 	{ 0 },
 };
 
-static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
+static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
 	{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
 	{ 0 },
 };
 
-static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
+static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
 	{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
 	{ 0 },
 };
@@ -61,9 +61,9 @@  static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst =
 	{ AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
 	{ AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
 	{ AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
+	{ AM3_L4LS_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
 	{ AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
 	{ AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
-	{ AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
 	{ AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
 	{ AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
 	{ AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
@@ -131,14 +131,14 @@  static const char * const am3_gpio0_dbclk_parents[] __initconst = {
 	NULL,
 };
 
-static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
+static const struct omap_clkctrl_bit_data am3_gpio0_bit_data[] __initconst = {
 	{ 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
 	{ 0 },
 };
 
 static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
 	{ AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
-	{ AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
+	{ AM3_L4_WKUP_GPIO0_CLKCTRL, am3_gpio0_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
 	{ AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
 	{ AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
 	{ AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h
index 894951541276..980fdc05c3d0 100644
--- a/include/dt-bindings/clock/am3.h
+++ b/include/dt-bindings/clock/am3.h
@@ -41,9 +41,9 @@ 
 #define AM3_RNG_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x90)
 #define AM3_AES_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x94)
 #define AM3_SHAM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xa0)
-#define AM3_GPIO2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xac)
-#define AM3_GPIO3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb0)
-#define AM3_GPIO4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb4)
+#define AM3_GPIO1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xac)
+#define AM3_GPIO2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb0)
+#define AM3_GPIO3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb4)
 #define AM3_TPCC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xbc)
 #define AM3_D_CAN0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xc0)
 #define AM3_D_CAN1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xc4)
@@ -69,7 +69,7 @@ 
 #define AM3_L4_WKUP_CLKCTRL_OFFSET	0x4
 #define AM3_L4_WKUP_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
 #define AM3_CONTROL_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
-#define AM3_GPIO1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
+#define AM3_GPIO0_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
 #define AM3_L4_WKUP_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
 #define AM3_DEBUGSS_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
 #define AM3_WKUP_M3_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
@@ -121,9 +121,9 @@ 
 #define AM3_L4LS_TIMER3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x84)
 #define AM3_L4LS_TIMER4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x88)
 #define AM3_L4LS_RNG_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x90)
-#define AM3_L4LS_GPIO2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xac)
-#define AM3_L4LS_GPIO3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb0)
-#define AM3_L4LS_GPIO4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb4)
+#define AM3_L4LS_GPIO1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xac)
+#define AM3_L4LS_GPIO2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb0)
+#define AM3_L4LS_GPIO3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb4)
 #define AM3_L4LS_D_CAN0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xc0)
 #define AM3_L4LS_D_CAN1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xc4)
 #define AM3_L4LS_EPWMSS1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xcc)
@@ -184,7 +184,7 @@ 
 
 /* l4_wkup clocks */
 #define AM3_L4_WKUP_CONTROL_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
-#define AM3_L4_WKUP_GPIO1_CLKCTRL	AM3_CLKCTRL_INDEX(0x8)
+#define AM3_L4_WKUP_GPIO0_CLKCTRL	AM3_CLKCTRL_INDEX(0x8)
 #define AM3_L4_WKUP_L4_WKUP_CLKCTRL	AM3_CLKCTRL_INDEX(0xc)
 #define AM3_L4_WKUP_UART1_CLKCTRL	AM3_CLKCTRL_INDEX(0xb4)
 #define AM3_L4_WKUP_I2C1_CLKCTRL	AM3_CLKCTRL_INDEX(0xb8)