From patchwork Mon Sep 26 05:10:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: b35362@freescale.com X-Patchwork-Id: 116359 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F0734B6F81 for ; Mon, 26 Sep 2011 16:17:49 +1000 (EST) Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R84VC-00055D-HZ; Mon, 26 Sep 2011 06:17:18 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1R84VC-0000Nu-5d; Mon, 26 Sep 2011 06:17:18 +0000 Received: from ch1ehsobe004.messaging.microsoft.com ([216.32.181.184] helo=ch1outboundpool.messaging.microsoft.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R84V7-0000NZ-Ty for linux-mtd@lists.infradead.org; Mon, 26 Sep 2011 06:17:15 +0000 Received: from mail43-ch1-R.bigfish.com (216.32.181.170) by CH1EHSOBE015.bigfish.com (10.43.70.65) with Microsoft SMTP Server id 14.1.225.22; Mon, 26 Sep 2011 06:17:09 +0000 Received: from mail43-ch1 (localhost.localdomain [127.0.0.1]) by mail43-ch1-R.bigfish.com (Postfix) with ESMTP id B2DF8D702F1; Mon, 26 Sep 2011 06:17:09 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail43-ch1 (localhost.localdomain [127.0.0.1]) by mail43-ch1 (MessageSwitch) id 1317017829262169_6361; Mon, 26 Sep 2011 06:17:09 +0000 (UTC) Received: from CH1EHSMHS011.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.253]) by mail43-ch1.bigfish.com (Postfix) with ESMTP id 3156E178004E; Mon, 26 Sep 2011 06:17:09 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS011.bigfish.com (10.43.70.11) with Microsoft SMTP Server (TLS) id 14.1.225.22; Mon, 26 Sep 2011 06:17:08 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.323.7; Mon, 26 Sep 2011 01:17:07 -0500 Received: from localhost (rock.ap.freescale.net [10.193.20.106]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p8Q6H5qK014999; Mon, 26 Sep 2011 01:17:06 -0500 (CDT) From: To: Subject: [PATCH] mtd/nand : workaround for Freescale FCM to support large-page Nand chip Date: Mon, 26 Sep 2011 13:10:06 +0800 Message-ID: <1317013806-23640-1-git-send-email-b35362@freescale.com> X-Mailer: git-send-email 1.6.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110926_021714_167892_4553EA1F X-CRM114-Status: GOOD ( 29.49 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.181.184 listed in list.dnswl.org] Cc: Liu Shuo , Artem.Bityutskiy@nokia.com, Li Yang , linux-mtd@lists.infradead.org X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Liu Shuo Freescale FCM controller has a 2K size limitation of buffer RAM. In order to support the Nand flash chip whose page size is larger than 2K bytes, we read/write 2k data repeatedly by issuing FIR_OP_RB/FIR_OP_WB and save them to a large buffer. Signed-off-by: Liu Shuo Signed-off-by: Li Yang --- drivers/mtd/nand/fsl_elbc_nand.c | 182 ++++++++++++++++++++++++++++++++++--- 1 files changed, 167 insertions(+), 15 deletions(-) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index a212116..183e532 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -76,6 +76,9 @@ struct fsl_elbc_fcm_ctrl { unsigned int oob; /* Non zero if operating on OOB data */ unsigned int counter; /* counter for the initializations */ char *oob_poi; /* Place to write ECC after read back */ + + char *buffer; + int page_size; /* the mutiple of 2048 */ }; /* These map to the positions used by the FCM hardware ECC generator */ @@ -151,6 +154,44 @@ static struct nand_bbt_descr bbt_mirror_descr = { }; /*=================================*/ +static void io_to_buffer(struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl, + int subpage, int off, int len, int oob) +{ + void *src, *dst; + + if (!len) + len = (oob ? 64 : 2048); + + if (oob) + dst = elbc_fcm_ctrl->buffer + elbc_fcm_ctrl->page_size + + subpage * 64 + off; + else + dst = elbc_fcm_ctrl->buffer + subpage * 2048 + off; + + src = elbc_fcm_ctrl->addr + (oob ? 2048 : 0) + off; + memcpy_fromio(dst, src, len); +} + +static void buffer_to_io(struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl, + int subpage, int off, int len, int oob) +{ + void *src, *dst; + + if (!len) + len = (oob ? 64 : 2048); + + if (oob) + src = elbc_fcm_ctrl->buffer + elbc_fcm_ctrl->page_size + + subpage * 64 + off; + else + src = elbc_fcm_ctrl->buffer + subpage * 2048 + off; + + dst = elbc_fcm_ctrl->addr + (oob ? 2048 : 0) + off; + + memcpy_toio(dst, src, len); + in_8(elbc_fcm_ctrl->addr); +} + /* * Set up the FCM hardware block and page address fields, and the fcm @@ -167,15 +208,14 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) elbc_fcm_ctrl->page = page_addr; - out_be32(&lbc->fbar, - page_addr >> (chip->phys_erase_shift - chip->page_shift)); - if (priv->page_size) { + out_be32(&lbc->fbar, page_addr >> 6); out_be32(&lbc->fpar, ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | (oob ? FPAR_LP_MS : 0) | column); buf_num = (page_addr & 1) << 2; } else { + out_be32(&lbc->fbar, page_addr >> 5); out_be32(&lbc->fpar, ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | (oob ? FPAR_SP_MS : 0) | column); @@ -187,7 +227,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) /* for OOB data point to the second half of the buffer */ if (oob) - elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512; + elbc_fcm_ctrl->index += mtd->writesize; dev_vdbg(priv->dev, "set_addr: bank=%d, " "elbc_fcm_ctrl->addr=0x%p (0x%p), " @@ -286,6 +326,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, struct fsl_lbc_ctrl *ctrl = priv->ctrl; struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; struct fsl_lbc_regs __iomem *lbc = ctrl->regs; + int i; elbc_fcm_ctrl->use_mdr = 0; @@ -314,6 +355,27 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, fsl_elbc_do_read(chip, 0); fsl_elbc_run_command(mtd); + + if (priv->page_size <= 1) + return; + + /* Continue to read the rest bytes if writesize > 2048 */ + io_to_buffer(elbc_fcm_ctrl, 0, 0, 0, 0); + io_to_buffer(elbc_fcm_ctrl, 0, 0, 0, 1); + + for (i = 1; i < priv->page_size; i++) { + /* + * Maybe there are some reasons of FCM hardware timming, + * we must insert a FIR_OP_NOP(0x00) before FIR_OP_RB. + */ + out_be32(&lbc->fir, FIR_OP_RB << FIR_OP1_SHIFT); + out_be32(&lbc->fbcr, 0); + fsl_elbc_run_command(mtd); + + io_to_buffer(elbc_fcm_ctrl, i, 0, 0, 0); + io_to_buffer(elbc_fcm_ctrl, i, 0, 0, 1); + } + return; /* READOOB reads only the OOB because no ECC is performed. */ @@ -322,13 +384,31 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" " 0x%x, column: 0x%x.\n", page_addr, column); - out_be32(&lbc->fbcr, mtd->oobsize - column); - set_addr(mtd, column, page_addr, 1); + out_be32(&lbc->fbcr, 64); + set_addr(mtd, 0, page_addr, 1); elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; + elbc_fcm_ctrl->index += column; fsl_elbc_do_read(chip, 1); fsl_elbc_run_command(mtd); + + if (priv->page_size <= 1) + return; + + if (column < 64) + io_to_buffer(elbc_fcm_ctrl, 0, 0, 0, 1); + + out_be32(&lbc->fpar, in_be32(&lbc->fpar) & ~FPAR_LP_MS); + for (i = 1; i < priv->page_size; i++) { + fsl_elbc_do_read(chip, 0); + out_be32(&lbc->fir, FIR_OP_RB << FIR_OP1_SHIFT); + out_be32(&lbc->fbcr, 2112); + fsl_elbc_run_command(mtd); + + if (column < (64 * (i + 1))) + io_to_buffer(elbc_fcm_ctrl, i, 0, 0, 1); + } return; /* READID must read all 5 possible bytes while CEB is active */ @@ -396,7 +476,14 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) | (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT); - if (priv->page_size) { + if (priv->page_size > 1) { + /* writesize > 2048 */ + out_be32(&lbc->fir, + (FIR_OP_CM2 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_WB << FIR_OP3_SHIFT)); + } else if (priv->page_size) { out_be32(&lbc->fir, (FIR_OP_CM2 << FIR_OP0_SHIFT) | (FIR_OP_CA << FIR_OP1_SHIFT) | @@ -453,8 +540,29 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, full_page = 1; } + if (priv->page_size > 1) { + buffer_to_io(elbc_fcm_ctrl, 0, 0, 0, 0); + buffer_to_io(elbc_fcm_ctrl, 0, 0, 0, 1); + } + fsl_elbc_run_command(mtd); + for (i = 1; i < priv->page_size; i++) { + elbc_fcm_ctrl->use_mdr = 1; + if (i == priv->page_size - 1) + out_be32(&lbc->fir, + (FIR_OP_WB << FIR_OP1_SHIFT) | + (FIR_OP_CM3 << FIR_OP2_SHIFT) | + (FIR_OP_CW1 << FIR_OP3_SHIFT) | + (FIR_OP_RS << FIR_OP4_SHIFT)); + else + out_be32(&lbc->fir, FIR_OP_WB << FIR_OP1_SHIFT); + out_be32(&lbc->fbcr, 0); + buffer_to_io(elbc_fcm_ctrl, i, 0, 0, 0); + buffer_to_io(elbc_fcm_ctrl, i, 0, 0, 1); + fsl_elbc_run_command(mtd); + } + /* Read back the page in order to fill in the ECC for the * caller. Is this really needed? */ @@ -541,7 +649,14 @@ static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) len = bufsize - elbc_fcm_ctrl->index; } - memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len); + if (mtd->writesize > 2048) + memcpy(&elbc_fcm_ctrl->buffer[elbc_fcm_ctrl->index], + buf, len); + else { + memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], + buf, len); + } + /* * This is workaround for the weird elbc hangs during nand write, * Scott Wood says: "...perhaps difference in how long it takes a @@ -587,7 +702,12 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) avail = min((unsigned int)len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index); - memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail); + if (mtd->writesize > 2048) + memcpy(buf, &elbc_fcm_ctrl->buffer[elbc_fcm_ctrl->index], + avail); + else + memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], + avail); elbc_fcm_ctrl->index += avail; if (len > avail) @@ -623,10 +743,16 @@ static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) return -EINVAL; } - for (i = 0; i < len; i++) - if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i]) - != buf[i]) - break; + if (mtd->writesize > 2048) + for (i = 0; i < len; i++) + if (elbc_fcm_ctrl->buffer[elbc_fcm_ctrl->index + i] + != buf[i]) + break; + else + for (i = 0; i < len; i++) + if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i]) + != buf[i]) + break; elbc_fcm_ctrl->index += len; return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO; @@ -655,6 +781,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) struct fsl_elbc_mtd *priv = chip->priv; struct fsl_lbc_ctrl *ctrl = priv->ctrl; struct fsl_lbc_regs __iomem *lbc = ctrl->regs; + struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; unsigned int al; /* calculate FMR Address Length field */ @@ -705,12 +832,17 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n", mtd->oobsize); + kfree(elbc_fcm_ctrl->buffer); + elbc_fcm_ctrl->buffer = NULL; + /* adjust Option Register and ECC to match Flash page size */ if (mtd->writesize == 512) { priv->page_size = 0; clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); - } else if (mtd->writesize == 2048) { - priv->page_size = 1; + } else if (mtd->writesize >= 2048) { + /* page_size = writesize / 2048 */ + priv->page_size = mtd->writesize >> 11; + setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); /* adjust ecc setup if needed */ if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == @@ -721,6 +853,15 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) &fsl_elbc_oob_lp_eccm0; chip->badblock_pattern = &largepage_memorybased; } + elbc_fcm_ctrl->page_size = mtd->writesize; + + /* re-malloc if pagesize > 2048*/ + if (mtd->writesize > 2048) { + elbc_fcm_ctrl->buffer = kmalloc(mtd->writesize + + mtd->oobsize, GFP_KERNEL); + if (!elbc_fcm_ctrl->buffer) + return -ENOMEM; + } } else { dev_err(priv->dev, "fsl_elbc_init: page size %d is not supported\n", @@ -888,6 +1029,17 @@ static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev) goto err; } elbc_fcm_ctrl->counter++; + /* + * Freescale FCM controller has a 2K size limitation of buffer + * RAM, so elbc_fcm_ctrl->buffer have to be used if writesize + * of chip is greater than 2048. + * We malloc a large enough buffer at this point, because we + * don't know writesize before calling nand_scan(). We will + * re-malloc later if needed. + */ + elbc_fcm_ctrl->buffer = kmalloc(4096 * 6, GFP_KERNEL); + if (!elbc_fcm_ctrl->buffer) + return -ENOMEM; spin_lock_init(&elbc_fcm_ctrl->controller.lock); init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);