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SCL:1; SRVR:MN2PR11MB3984; H:MN2PR11MB4448.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 3Sgtao9C5IkAV4mkQwuXGU/gOJa2ID2j5mWxqbKXrTOLufoQ6i7/rVrYy2pjBmJ6tX1W2L8BwzCa6vKQyaz05bJmTFFyKLY1KtcLpc4ENxPPFEHBmaMefxjIjsYeJSYUqZlWzJJs9xjqYQacqrSMd0V5rbcJnkoyy02rHLM4xZbf0zGv2q1ZaaOMg28k9g/7tYZOZ8cGSVLxl7rehWjgMhfkvsG31fabjLEbc2Ff1FDn9F/02nPiGyhooverlH47FS5tdm1IGZlHObW2E0/STDQZg4+pJrpx85Zw2dP+buDofAstZb1Q7Y9IaNsg5/yIP0IynVnGI6BG383G1aHG8noIuy864ar3ErdQjQMn3flrxxavGXxFNpYXg0TYKhgG8abzJxRrKLCf+0XVBbpGxlN5HA3/adXmFJa+v4gdRrc= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 15f1b520-defa-4e35-b53b-08d73b877c20 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Sep 2019 15:55:38.8204 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4s6URAcG5SJe8UhN08LZ8jppxGQKmkWg1BWHtEFI4v7HQfuzBRWfMyAuM5CiOL1Lq8qDnm2BHVWQ+kESNPRJmJuxBY4032PCizjYK60X6wM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3984 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-aspeed@lists.ozlabs.org, Tudor.Ambarus@microchip.com, linux-kernel@vger.kernel.org, vz@mleia.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, computersforpeace@gmail.com, dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" From: Tudor Ambarus Rename method to a generic name: spi_nor_sr1_bit6_quad_enable(). Use spi_nor_write_sr1_and_check(). Now we check the validity of all the eight bits of the Status Register, not just of the SR1_QUAD_EN_BIT6. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 34 ++++++++++------------------------ include/linux/mtd/spi-nor.h | 2 +- 2 files changed, 11 insertions(+), 25 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 4a513ed13807..2f79923e7db5 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1938,16 +1938,15 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) } /** - * macronix_quad_enable() - set QE bit in Status Register. + * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status + * Register 1. * @nor: pointer to a 'struct spi_nor' * - * Set the Quad Enable (QE) bit in the Status Register. - * - * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. + * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. * * Return: 0 on success, -errno otherwise. */ -static int macronix_quad_enable(struct spi_nor *nor) +static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) { int ret; @@ -1955,25 +1954,12 @@ static int macronix_quad_enable(struct spi_nor *nor) if (ret) return ret; - if (nor->bouncebuf[0] & SR_QUAD_EN_MX) + if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) return 0; - nor->bouncebuf[0] |= SR_QUAD_EN_MX; + nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; - ret = spi_nor_write_sr(nor, &nor->bouncebuf[0], 1); - if (ret) - return ret; - - ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]); - if (ret) - return ret; - - if (!(nor->bouncebuf[0] & SR_QUAD_EN_MX)) { - dev_err(nor->dev, "Macronix Quad bit not set\n"); - return -EIO; - } - - return 0; + return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0], 0xFF); } /** @@ -2277,7 +2263,7 @@ static void gd25q256_default_init(struct spi_nor *nor) * indicate the quad_enable method for this case, we need * to set it in the default_init fixup hook. */ - nor->flash.quad_enable = macronix_quad_enable; + nor->flash.quad_enable = spi_nor_sr1_bit6_quad_enable; } static struct spi_nor_fixups gd25q256_fixups = { @@ -3661,7 +3647,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, case BFPT_DWORD15_QER_SR1_BIT6: nor->flags &= ~SNOR_F_HAS_16BIT_SR; - flash->quad_enable = macronix_quad_enable; + flash->quad_enable = spi_nor_sr1_bit6_quad_enable; break; case BFPT_DWORD15_QER_SR2_BIT7: @@ -4558,7 +4544,7 @@ static int spi_nor_setup(struct spi_nor *nor, static void macronix_set_default_init(struct spi_nor *nor) { - nor->flash.quad_enable = macronix_quad_enable; + nor->flash.quad_enable = spi_nor_sr1_bit6_quad_enable; nor->flash.set_4byte = macronix_set_4byte; } diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index fc3a8f5209f0..3a835de90b6a 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -133,7 +133,7 @@ #define SR_E_ERR BIT(5) #define SR_P_ERR BIT(6) -#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ +#define SR1_QUAD_EN_BIT6 BIT(6) /* Enhanced Volatile Configuration Register bits */ #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */